創新的全數位頻率合成器設計分析與實現

Design, Implementation and Analysis of A Novel Digital Frequency Synthesize

楊穎元(Ying-Yuan Yang)

指導教授 ： 趙燿庚

元智大學/工程學院/通訊工程學系/碩士(2006年)

https://doi.org/10.6838/YZU.2006.00009

摘要

近年來電腦產業蓬勃發展，系統不斷的提升速度及複雜度，同步訊號的快速穩定與運用範圍日趨重要。因此，如何提升同步系統的頻寬及穩定度，成為熱門的話題。
“Flying Adder”架構，其最大的noice來自於輸入訊號的不匹配，由於使用太多的延遲階數產生輸入訊號，而造成在佈局上的困難，因此，減少階數，也是一個重要的議題。
頻率合成器，可以使用在許多的應用，例如：無線通訊系統，LCD 驅動…等，本篇論文係基於一全數位頻率合成器的架構來作分析，並加以改良，期望能設計具有益於穩定度高、快速鎖向與高頻寬的電路架構。

關鍵字

頻率合成器

並列摘要

Because the industry of the computer grows vigorously in recent years and system is increased the speed and complexity constantly, the fast stability of the synchronous signal and locking range are becoming more important. So, how to improve bandwidth and stability with synchronous system becomes the hot topic.
The heaviest noise of "Flying Adder" Structure comes from the signal mismatch because the layout mismatch of the multiple delay stages. Thus, the issue is important to reduce the number of delay stages.
The frequency synthesizer can use in a lot of application, for example: the wireless communication system, LCD drives, etc. This thesis is based on the structure of all digital frequency synthesizer which is improved and expect the circuit structure by design benefits of having on high stability, fast lock time and wide bandwidth.

並列關鍵字

frequency synthesizer

參考文獻

[1] H. Mair and L. Xiu, “An architecture of high performance frequency and phase synthesis,” IEEE J. Solid-State Circuits, vol. 35, pp. 835–846,June 2000.

[2] L. Xiu and Z. You, “An flying-adder architecture of frequency and phase synthesis with scalability,” IEEE Trans. VLSI Syst., vol. 10, pp. 637–649,Oct. 2002.

[4] L. Xiu and Z.You, “A flying-adder frequency synthesis architecture of reducing VCO stages,” IEEE Trans.VLSI Syst.,vol. 13, no. 2,, FEBRUARY 2005.

[7] Keshab K. Parhi - VLSI Digital Signal Processing Systems : Design and Implementation

[8]張智鈞，”新的全數位頻率與相位合成器設計與分析”，碩士論文，元智大學，通訊工程研究所，2005。