使用頻率倍率計算器之全數位頻率合成器

An All-Digital Frequency Synthesizer Using a Frequency Ratio Calculator

呂昀芝(Yun-Chih Lu)

指導教授 ： 陳怡然

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2022年)

https://doi.org/10.6342/NTU202200407

摘要

全數位頻率合成器近年來一直是個熱門的主題，數位電路特性能快速將設計的替換到不同製程上。本論文提出一全新的全數位頻率合成器架構，有別於以往常見的在時域上運用利用二元式相位偵測器或是時間數位時間轉換器來偵測輸入頻率與參考頻率之間的時間差，本論文提出頻率倍率計算器，透過數學的統計運算方式直接計算輸入訊號與參考頻率之間的倍率，不受限於製程提供的最小時間解析度單一反相器的延遲時間精準度，在不考慮面積和功耗的情況下，根據數學模型推論可以依要求幾乎無限制的提高時間解析度直到應用所需要的量級。
使用90奈米CMOS製程實現的全數位頻率合成器，晶片操作面積為長820微米寬650微米，根據量測結果，在1.2 V供應電壓下，功率消耗為17.5 毫瓦，鎖定頻率範圍為10.76到11.34 GHz，鎖定時間約為55個參考頻率的時間，1.12微秒左右。

關鍵字

全數位頻率合成器 ； 頻率倍率計算器 ； 快速鎖定 ； 時間數位轉換器

並列摘要

All-digital frequency synthesizers have become popular because of easy adaptation to different CMOS technology. The conventional approach of developing fractional-N PLLs utilizes bang-bang phase frequency detector (BBPFD) and time-to-digital converter (TDC) to detect the timing difference between the scaled signal and reference clock. This dissertation presents the first all-digital frequency synthesizer with frequency ratio calculator (FRC) as an alternative function block to BBPFDs and TDCs in digital PLLs for fast locking.
The all-digital frequency synthesizer is implemented in 90 nm CMOS technology. The core chip size is 0.82 × 0.65 mm2. The all-digital frequency synthesizer was tested under a supply voltage of 1.2V and power consumption is 17.5 mW. In the frequency range between 10.76 GHz and 11.34 GHz, the measured settling time is about 55 reference clock cycles ( 1.12 us ).

並列關鍵字

all-digital frequency synthesizer ； frequency ratio calculator (FRC) ； fast locking technique ； time-to-digital converter (TDC)

參考文獻

[1] A. Bazrafshan, M. Taherzadeh-Sani, and F. Nabki, “A 0.8-4 GHz software-defined radio receiver with improved harmonic rejection through non-overlapped clocking,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 10, pp. 3186–3195, Oct. 2018.

[2] F. T. Gebreyohannes, et al., “All-digital transmitter architecture based on two-path parallel 1-bit high pass filtering DACs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 11, pp. 3956–3969, Nov. 2018.

[3] A. B. Grebene and H. R. Camenzind, “Phase Locking As A New Approach For Tuned Integrated Circuits,” in Proc. IEEE Solid-State Circuits Conf. Digest of Technical Papers, pp. 100-101, Feb. 1969.

[4] X. Gao, et al., “A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2,“ IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009.

[5] B. Razavi, “A study of injection locking and pulling in oscillators,“ IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sept. 2004.