小面積之高速32-Bit AES的FPGA設計

Low Area with High Speed 32-Bit AES Design in FPGA

陳奕丞(Yi-Cheng Chen)

指導教授 ： 黃奇武 ； 張吉正

國立臺灣師範大學/科技學院/工業教育學系/碩士(2009年)

摘要

近幾年來進階加密演算法AES(Advanced Encryption Standard)針對縮小面積與提升頻率之議題而時常被廣泛的討論，為達上述之方向，本文將AES演算法內含的SubBytes和MixColumns乘法運算改用以雙埠記憶體（Dual Port Block RAMs）做查表取代運算，除此之外，在ShiftRows方面，使用旋轉暫存器(rotate register)來取代memories，使整個AES硬體電路佔用面積可小到118 Slices、而產率(Throughput)最快可達到213 Mbps(Mega bit per second)，與文獻上最好之數據163 Slices與208 Mbps相比，面積減少27%、速度增加1.02倍。 小面積之高速32-Bit AES除了做一般文字加解密外，本文嘗試將其應用於需大量資料運算的靜態影像加解密，從模擬結果觀察之，影像加解密的視覺效果較文字更為明顯。 本篇論文利用Xilinx公司所提供的ISE 9.2i為設計平台，利用VHDL進行設計，第一章緒論介紹研究背景、研究目的與研究動機及介紹AES在目前產品化的應用，第二章說明完整的AES演算法流程及過程介紹，第三章介紹IEEE上所發表的相關文獻探討，介紹以記憶體和邏輯電路架構實現的方式，第四章利用第三章所提出的一些架構及特性配合FPGA電路需求去做設計，第五章將實現的電路去做模擬與測試，並做文字與影像上的加密，第六章結論及未來工作。

並列摘要

Recently the development of the AES algorithm has been focused on minimizing its area and enhancing its speed. This paper uses Dual Port Block RAMs to perform multiplication that was done by SubBytes and MixColumns, and rotate registers instead of memories in ShiftRows in order to lower the hardware area to 118 slices and maximize the throughput to 213 Mbps. Compared to 163 Slices and 208 Mbps on other papers the area has decreased 27% and the speed has increased 1.02 times.
Besides Encrypting/Decrypting phrases, the low area 32-Bit AES, we implement it on picture encryptions that require large amount of data processing. From simulation results picture encryptions have a better effect than phrase encryption.
We use ISE9.2i of Xilinx as a platform and design using VHDL. Section one gives some background, the main purpose of this project, and some products and implementations of AES. Section two introduces the procedure of the AES algorithm. Section three shows some related studies on IEEE and the construction of memory and logic circuits, section four then realizes these circuits on FPGA. Section five is the simulation with the encryption/decryption, and lastly section six concludes our work and provides some future works.

並列關鍵字

AES ； FPGA ； Dual Port Block RAM

參考文獻

NIST. Institute of Standards and Technology, 「Specification for the Data encryption Standard(DES),」 FIPS PUB46-3, October 1999.

Tim Good and Mohammed Benaissa, "Very small FPGA application-specificinstruction processor for AES," IEEE Trans. Circuit and System, Vol. 53, no. 7, pp. 1477-1486, July 2006.

Pawel Chodowiec and Kris Gaj, 「Very Compact FPGA Implementation of the AES Algorithm,」 CHES 2003, Vol. 2779, September 2003.

Gael Rouvroy, Francois-Xavier Standaert, Jean-Jacques Quisquater and Jean-Didier Legat, 「Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications,」 ITCC 2004, Vol. 02, pp. 583-587, August 2004.

Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, and Leonel Sousa, 「Reconfigurable Memory Based AES Co-Processor,」 IPDPS 2006, April 2006.