32位元小面積之嵌入式AES的FPGA設計與影像應用

A 32-bit Low Area Embedded AES FPGA Design for Image Application

張國煌(Kuo-Huang Chang)

指導教授 ： 黃奇武 ； 張吉正

國立臺灣師範大學/科技學院/應用電子科技研究所/碩士(2009年)

摘要

高等加密標準(Advanced Encryption Standard, AES)硬體實現在現場可程式化閘陣列(FPGA)與特殊用途積體電路(ASIC)已經被很廣泛的討論，尤其是如何達到數十億產率的議題；然而在嵌入式硬體的應用上，低產率與小面積的設計在近幾年也開始被研究。
　　本研究提出一個小面積的硬體電路，採用32位元的架構來實現AES-128的規格，其中包含2組移位暫存器(Shift Register)來完成移列轉換(ShiftRow)的動作；並利用晶片內建的Block RAM來放置整合資料，完成位元組替換(SubByte)與混行運算(MixColumn)的動作；而以軟體來取代硬體的金鑰擴展(KeyExpansion)，來節省電路面積。透過上述所提出的方式在FPGA上所完成的實驗數據，其資源消耗為110個Slice、速度可達到75Mhz(每秒可處理29張640×480大小的彩色影像)，是在目前文獻中面積最小的設計。
　　為實現影像加解密的應用，本研究分別使用兩種方式來與上述32位元AES核心電路整合，其一為結合嵌入式系統與IP core的架構，屬於軟體與硬體的搭配；另一為只用硬體描述語言(HDL)來實現，較偏向硬體電路來控制。

關鍵字

高等加密標準 ； 現場可程式化閘陣列 ； 影像處理

並列摘要

Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC have been intensely discussed, especially in high-throughput of Giga bit per second (Gbps). However, lower throughput and area designs have also been investigated in the recent years for embedded hardware applications.
　　This paper presents a 32-bit AES implementation with a speed of 75MHz (29 640x480 frames per second) and low area of 110 slices, which is the smallest design among literature reports. There are two Shift-Registers for ShiftRow; a built-in Block RAM for SubByte and MixColumn; KeyExpansion utilizing software instead of hardware.
　　In order to realize image encryption/decryption, we combine the 32-bit AES with two types of implements. First, the Embedded System with a MicroBlaze core which uses software and hardware codesign. Second, using HDL hardware description language, which is mainly a hardware implementation.

並列關鍵字

AES ； FPGA ； Embedded System ； MicroBlaze

參考文獻

[1] NIST. Announcing the advanced encryption standard (AES), FIPS 197. Technical report, National Institute of Standards and Technology, November 2001.

[2] T. Good and M. Benaissa “Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment),” in the Institution of Engineering and Technology, vol. 1, no. 1, pp. 1–10, April 2007.

[3] A. Hodjat, “Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors,” IEEE Trans. Computers, vol. 55, no. 4, pp. 366–372, April 2006.

[4] A. Hodjat and I. Verbauwhede, “Interfacing a high speed crypto accelerator to an embedded cpu,” In Proc. 38th Asilomar Conference on Signals, Systems, and Computers, vol. 1, pp. 488–492, November 2004.

[5] Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, and Hung-Yun Tai, “The FPGA Implementation of 128-bits AES Algorithm Based on Four 32-bits Parallel Operation,” ISDPE 2007, pp. 462–464, November 2007.