鑭摻入極薄氧化鋯高介電係數閘極介電層之效應

The Effect of Lanthanum (La) Incorporation in Ultra-Thin ZrO2 High-k Gate Dielectrics

周益賢

指導教授 ： 劉傳璽 ； 程金保

國立臺灣師範大學/科技學院/機電科技研究所/碩士(2010年)

摘要

本研究主要是探討將La摻入ZrO2薄膜的影響，也就是研究高介電極薄氧化層薄膜ZrLaO的電性以期能應用在邏輯電路的科技上。本研究之薄膜是利用射頻濺鍍以及直流濺鍍系統將氧化鋯 (ZrO2)以及鑭金屬 (La)兩種靶材共鍍下所製備而成。純的ZrO2薄膜在沉積完薄膜後再進行650°C與 850°C在氮氣中的快速熱退火，之後再將鋁電極鍍上，使其成為MOS電容器結構後，比較其在不同的退火溫度下所表現出來的特性，試片皆有以橢圓儀以及高解析度的穿透式電子顯微鏡來獲得薄膜的物理厚度。透過X光繞射分析來獲得ZrO2以及ZrLaO薄膜在退火後是否有結晶相產生。電性方面，本實驗有量測許多薄膜的電性數據包括在不同的量測溫度下所得到的漏電流值、由C-V所得之介電係數、平帶電壓的偏移量、薄膜的漏電流傳導機制以及蕭基能障等。

關鍵字

高介電係數介電層 ； 界面層 ； 傳導機制 ； 氧化鑭鋯

並列摘要

This study is mainly to investigate the La doping effect on the electrical properties of ultra-thin La-doped ZrO2 (denoted by ZrLaO) films for high-k gate dielectric applications of advanced logic technologies. In this work, ZrLaO films were co-deposited on p-type Si wafers by RF magnetron sputtering in the Ar ambient at room temperature, where ZrO2 and La targets utilized RF power and DC power, respectively, for sputtering. For comparison, ZrO2 films of similar physical thickness were also independently formed on Si wafers. A post-deposition annealing (PDA) was then performed in N2 ambient at 650℃ and 850℃. To form MOS structures, Al was sputtered as the top electrode, followed by annealing at 400℃ in N2. The film thickness was determined by ellipsometry and high-resolution transmission electron microscopy (HRTEM). The crystallization phase of ZrO2 and ZrLaO after PDA was investigated by X-ray diffraction (XRD). The electrical properties of ZrO2 with or without La incorporation were also analyzed and compared, including leakage current measured at 300-450 K, dielectric constant, flat-band voltage shift, current conduction behavior, and Schottky barrier height.

並列關鍵字

ZrLaO ； high-k dielectric ； interfacial layer ； conduction mechanism

參考文獻

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