具預先偵測動態量化之三角積分調變器設計

The ΔΣ Modulator with Pre-Detective Dynamic Quantization

賴宏璟

指導教授 ： 郭建宏

國立臺灣師範大學/科技學院/應用電子科技學系/碩士(2011年)

摘要

因應現今積體電路設計業的製程技術已邁入奈米科技時代，含有數位與類比電路的低功率混合信號積體電路設計考量也跟著不同。數位電路設計可以有顯著的進步，然而類比電路設計卻被電晶體導通電壓未等比例改進而有所局限。為有效地增加類比數位轉換器精密度並降低耗能於電源供應電壓下降狀況下。本論文介紹兩種類比數位三角積分調變器，分別被推導設計適用於中或低頻區段。首先介紹以學者所提出的強健型串疊三角積分調變器為主體，以減少後端數位濾波器的使用，接著引進數位輸入前饋技術於調變器第一級，將量化誤差傳入第二級後，藉由後端數位減法器的運用，使得所提強健型串疊三角積分調變器使用輸入數位前饋可完整消除第一級的量化誤差。再者提出非純虛數共軛零點落於中心頻率附近，可再次強化輸出解析度。另外搭配部份取樣以及雙取樣技術來降低操作頻率以及各級使用低失真架構，用以減輕電路元件設計負擔。最後，藉由線性軟體模擬架構特性，本論文所提出之六階強健疊接型複數零點帶通三角積分調變器使用延遲數位前饋技術可達訊號雜訊含失真比105.67dB於10.7MHz輸入頻率與200kHz的信號頻寬。另外，本論文亦提出新的多位元量化器的輸出組成表現，藉由偵測器預先判斷訊號走向，接著控制後端動態量化器進行有效的高解析度量化，配合回授補償恢復完整的量化輸出，成功地減少高位元量化器元件過多且複雜的問題。由TSMC 0.18μm 1P6M標準製程製造預計可達訊號雜訊含失真比86.12dB以上。上述三角積分調變器使用本論文所提出之增益強化電流鏡型AB類運算放大器以及時脈平均演算法，並且搭配低供應電壓1.2V來實現。

關鍵字

強健型串疊三角積分調變器 ； 輸入數位前饋 ； 複數零點帶通三角積分調變器 ； 動態量化器 ； 增益強化電流鏡型AB類運算放大器 ； 時脈平均演算法

並列摘要

In this paper, a sixth-order sturdy multi-stage noise shaping (SMASH) bandpass delta-sigma (ΔΣ) modulator with delaying digital input feedforward structure is presented. The second-order ΔΣ modulator with cascade integrators and distributed feedforward (CIFF) is utilized in each stage to reduce the signal swing. Hence, the requirement of Opamp and the power consumption of circuits can be reduced due to the suppression of the signal swing and the discarding of the digital cancellation filters. One pair of complex zeros is designed within signal bandwidth to effectively suppress the noise floor of the presented modulator. The sub-sampling technique is adopted to reduce the clock frequency and the requirement of Opamp. Simulation results confirm the feasibility of the proposed SMASH CIFF bandpass ΔΣ modulator with delaying DFF structure and the signal-to-noise plus distortion ratio (SNDR) could reach 105.56dB in a 200 kHz of signal bandwidth centered at 10.7 MHz. Besides, another contents presented a dynamic ΔΣ modulator with pre-detective capability. The transmitted signal before quantizing could be detected first. The dynamic quantizer would follow the signal by adjusting different reference voltage during multi-bit quantization. Compare with traditional multi-bit quantization, the number of hardware and complexity would reduce. A super class AB gain enhanced current mirror OTA would also insert in the presented ΔΣ modulator to increase the slew rate in the low voltage operation. The proposed ΔΣ modulator designed by TSMC 0.18μm 1P6M process and consumed 400μW from a 1.2-V supply voltage. The SNDR could reach at least 86.12 dB in a 25 kHz of signal bandwidth centered at 8.9 kHz.

並列關鍵字

SMASH ； CIFF ； complex zeros bandpass ΔΣ modulator ； dynamic quantizer ； class AB gain enhanced current mirror OTA ； CLA

參考文獻

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