射頻功率放大器之靜電放電防護設計

On-Chip ESD Protection Design for Radio-Frequency Power Amplifier

李冠儀(Li Guan-Yi)

指導教授 ： 林群祐

國立臺灣師範大學/科技與工程學院/電機工程學系/碩士(2017年)

https://doi.org/10.6345/NTNU202202620

摘要

本論文旨在利用嵌入矽控整流器之串接二極體來完成大訊號擺幅功率放大器的靜電放電防護設計，為了比較所提出的靜電放電防護電路的優劣性，也設計了串接二極體以及二極體觸發矽控整流器兩種靜電放電防護電路來提供比較。
為了驗證所提出的靜電放電防護電路在實際電路上的效能，本論文也設計了一個功率放大器電路來搭配此次所設計的三種靜電放電防護電路。實驗結果顯示，嵌入矽控整流器之串接二極體不會造成訊號的衰減及失真，且能夠有效的保護功率放大器。
在本論文中所設計的電路皆使用0.18-μm CMOS製程完成。並在實際的量測中發現，搭配串接二極體寄生矽控整流器的功率放大器電路能承受7 kV以上人體放電模式之靜電放電測試。

關鍵字

靜電放電防護 ； 矽控整流器 ； 串接二極體 ； 射頻功率放大器

並列摘要

In this thesis, the diode string with embedded silicon-controlled rectifier (DSSCR) is designed to provide electrostatic discharge (ESD) protection of radio-frequency (RF) power amplifiers (PAs). To examine and evaluate the performance of the DSSCR, ESD protection circuits using the diode string (DS) and the diode-triggered SCR (DTSCR) are also designed and implemented for comparison with the proposed DSSCR protection circuit.
To validate the effectiveness of the designed ESD protection circuits, radio-frequency power amplifiers which equipped with the above-mentioned ESD protection circuits were designed and fabricated in this research. The measured results show that the protection circuit using DSSCR will not cause undesired signal degradation and distortion, and meanwhile can offer instant and effective protection to the RF PAs.
All of the ESD protection circuits designed in this thesis were fabricated using 0.18-um CMOS process. It is found in measurement that the RF PA equipped with the DSSCR protection circuit can bear 7-kV human-body-model (HBM) test.

並列關鍵字

Electrostatic discharge protection ； silicon-controlled rectifier ； diode string ； power amplifier

參考文獻

[1] A. Amerasekera and C. Duvvury, ESD in silicon integrated circuits. John Wiley & Sons, 2002.

[2] A. Wang, On-chip ESD protection for integrated circuits. Kluwer, 2002.

[3] P. Mak and R. Martins, “High-/mixed-voltage RF and analog CMOS circuits come of age,” IEEE Circuits Syst. Mag., vol. 10, no. 4, pp. 27–39, Fourth Quarter, 2010.

[4] M.-H. Tsai, Shawn S.-H. Hsu, F.-L. Hsueh, and C.-P. Jou, “A multi-ESD-path low-noise amplifier with a 4.3-A TLP current level in 65-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 12, pp. 4004-4011, Nov. 2010.

[5] Y.-W. Hsiao and M.-D. Ker, “A 5-GHz differential low-noise amplifier with high pin-to-pin ESD robustness in a 130-nm CMOS process,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 5, pp. 1044-1053, Apr. 2009.