24-GHz低雜訊放大器之靜電放電防護設計

On-Chip ESD Protection Design for 24-GHz LNA

林孟霆(Lin Meng-Ting)

指導教授 ： 林群祐

國立臺灣師範大學/科技與工程學院/電機工程學系/碩士(2017年)

https://doi.org/10.6345/NTNU202203079

摘要

本論文主旨為應用於射頻積體電路之全晶片靜電防護電路，本論文設計了兩種應用於高頻積體電路的靜電放電防護設計，並與先前論文所提出的傳統防護電路來做比較。所下線之晶片皆使用0.18um CMOS製程。

傳統靜電放電箝制電路已被廣泛應用於靜電放電防護設計之中，然而其高佈局面積在先進製程中往往會是個麻煩，因此本篇論文利用矽控整流器低佈局面積與優秀靜電防護能力特性，來加以改善傳統電路，而矽控整流器的閂鎖效應與導通速度過慢問題，本論文也提出了解決方法；本論文提出使用內嵌入式矽控整流器二極體串來改良原先P型與N型二極體的靜電放電能力，透過量測結果比較，本論文提出的兩種靜電放電防護設計皆能在單一面積下提供最佳的靜電耐受度並擁有且較低損耗值。

為了驗證靜電防護電路應用於高頻電路的實際功用，本論文也設計了24GHz低雜訊放大器並搭配適當尺寸的防護電路，在量測結果中，本論文所提出的防護設計並不會影響高頻電路之響應。

關鍵字

靜電放電 ； 矽控整流器 ； 低雜訊放大器

並列摘要

This essay is to design an effective whole-chip ESD protection circuits for RF integrated circuit. In this essay, two types of ESD protection designs, which apply to RF integrated circuits has been proposed and compared with conventional ESD protections. All of circuits in this essay are fabricated in 0.18-um CMOS process.

The conventional power-rail ESD clamp circuit has been used widely in ESD protection designs. However, the high layout area of conventional circuit is an issue in advanced process. Therefore, using silicon-controlled rectifier (SCR) with low layout area and excellent ESD protection ability improves the issue of the conventional power-rail ESD clamp circuit that is high layout area. Furthermore, solutions of the latch-up problem and slow-trigger-on speed of SCR have been proposed. In this essay, using the diode string with embedded SCR improves the issue of p-type and n-type diodes. Through the comparison of measurement results, two types of ESD protection designs can provide the best ESD robustness and the lowest loss at unit area.

In order to verify the practical function of ESD protection circuit on RF circuit, the low-noise amplifier (LNA) with the appropriate size of ESD protection circuit has been designed. In measurement results, proposed designs do not affect the RF performance.

並列關鍵字

Electrostatic discharge ； silicon-controlled rectifier ； low-noise amplifier

參考文獻

[1] S. Voldman, ESD Phtsics and Devices, John Wiley & Sons, 2005.

[2] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S. Kao, “ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness,” in Proc. IEEE Radio Frequency Integrated Circuit Symp., 2002, pp. 427-430.

[3] L. Li, H. Liu, Z. Yang, L. Chen, “A novel co-design and evaluation methodology for ESD protection in RFIC,” Microelectronics Reliability, vol. 52, pp. 2632–2639, July 2012.

[4] M.-D Ker, C.-Y. Lin, and Y.-W. Hsiao, “Overview on ESD protection designs of low parasitic capacitance for RFICs in CMOS technologies,” IEEE Trans. Device and Materials Reliability, vol. 11, no. 2, pp. 207-218, Jun. 2011.

[5] M.-D. Ker and C.-M. Lee, “ESD protection design for Giga-Hz RF CMOS LNA with novel impedance-isolation technique,” in Proc. EOS/ESD Symp., 2003, pp. 204–213.