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  • 學位論文

28GHz砷化鎵增強型pHEMT功率放大器與PIN二極體切換器設計

Design of a 28 GHz GaAs E-mode pHEMT Power Amplifier and a 28 GHz PIN diode Switch

指導教授 : 蔡政翰

摘要


第一顆電路為內具線性器之28 GHz二級功率放大器,透過傳輸線匹配網路達成輸出功率阻抗匹配、輸入共軛匹配之效果。當VG = 0.5 V時,且線性器為關閉狀態(Vctrl = 0 V)時,在頻率為28 GHz下,其功率增益(Power gain)約為21.16 dB,飽和輸出功率Psat約為24.63 dBm,1-dB增益壓縮點之輸出功率(OP1dB)約為24.01 dBm,最大功率附加效率Peak PAE約為36.41 %,而當線性器為開啟狀態((Vctrl1 = 0.35 V、Vctrl2 = 0.15 V)且頻率為28 GHz時,IMD3在-40 dBc時的輸出功率為16 dBm,整體晶片佈局面積為1 mm × 2 mm。 第二顆電路為28 GHz PIN二極體切換器,採用四分之一波長線的SPDT架構。當操作頻率為28 GHz且VON為-4 V、VOFF為1.3 V時, 插入損耗約為2.15 dB,輸入輸出反射損耗(S11、S22)分別為14.07 dB與9.92 dB,0.1-dB增益壓縮點之輸入功率(IP0.1dB)約為17 dBm,整體晶片佈局面積為1 mm × 1 mm。

關鍵字

功率放大器 線性器 切換器 28 GHz Ka頻帶

並列摘要


First, 28 GHz two-stage power amplifier with a built-in linearizer achieves output power matching and input conjugate matching through a transmission line matching network. When VG = 0.5 V and the linearizer is off (Vctrl = 0 V), the power gain at 28 GHz is 21.16 dB, the saturated output power (Psat) is 24.63 dBm, the output power at 1-dB gain compression point (OP1-dB) is 24.01 dBm, and the maximum power added efficiency (PAE) is 36.41 %. Moreover, when the linearizer is on (Vctrl1 = 0.35 V, Vctrl2 = 0.15 V) and the frequency is 28 GHz, the output power of IMD3 is 16 dBm at -40 dBc and the chip size is 1 mm × 2 mm. Second, a 28 GHz PIN diode switch adopts SPDT architecture with quarter wavelength lines. When operating at 28 GHz with VON at -4 V and VOFF at 1.3 V, the insertion loss is 2.15 dB, the input and output reflection losses (S11 and S22) are 14.07 dB and 9.92 dB respectively, and the input power at the 0.1-dB gain compression point (IP0.1dB) is 17 dBm, and the chip size is 1 mm × 1 mm.

並列關鍵字

Power Amplifier Linearizer switch 28 GHz Ka band

參考文獻


[1] T. Cameron, "Bits to Beams–RF Technology Evolution for 5G mmwave Radios," Analog Devices, Norwood, MA, USA, Tech. Rep, 2019.
[2] W.-C. Huang, J.-L. Lin, Y.-H. Lin, and H. Wang, "A K-band power amplifier with 26-dBm output power and 34% PAE with novel inductance-based neutralization in 90-nm CMOS," in 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018: IEEE, pp. 228-231.
[3] Y. Chang, B.-Z. Lu, Y. Wang, and H. Wang, "A Ka-band stacked power amplifier with 24.8-dBm output power and 24.3% PAE in 65-nm CMOS technology," in 2019 IEEE MTT-S International Microwave Symposium (IMS), 2019: IEEE, pp. 316-319.
[4] S. N. Ali, P. Agarwal, S. Mirabbasi, and D. Heo, "A 42–46.4% PAE continuous class-F power amplifier with C gd neutralization at 26–34 GHz in 65 nm CMOS for 5G applications," in 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2017: IEEE, pp. 212-215.
[5] K. Wang, Y. Yan, and X. Liang, "A K-band power amplifier in a 0.15-um GaAs pHEMT process," in 2018 IEEE MTT-S International Wireless Symposium (IWS), 2018: IEEE, pp. 1-3.

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