以0.18微米製程設計應用於Ku波段之寬頻帶低雜訊放大器

A Ku-Band Wideband Low-Noise Amplifier Design in 0.18-µm CMOS Process

馬辰璘(SIDDARTH RAI MAHENDRA)

指導教授 ： 劉 萬 榮

國立臺北大學/電機資訊學院/電機工程研究所/碩士(2010年)

摘要

無資料

關鍵字

Broadband, Ku-band, LNA, Low-noise amplifier, RF IC, Wideband.

並列摘要

The frequency band from 12-GHz to 18-GHz referred to as the Ku-band has been used for Satellite communications, Weather prediction and other similar such applications as published by the Federal Communications Commission (FCC), which is an independent agency of the United States government. The purpose of this thesis is to aim to design a wideband low-noise amplifier (LNA) across the entire band of operation in the Ku-band. We know that the LNA is the first module in the receiving path of a transceiver and it affects the performance of the signal bandwidth, noise figure, and power dissipation of the entire receiver system. Also, the strict matching constraint of matching to a given impedance value across the wide operating band is difficult to achieve and requires several area consuming inductors which degrade the noise figure of the LNA circuit significantly. Hence, we must try to reduce the noise figure and together decrease the power consumption of the LNA circuit while providing a high-enough power-gain that is acceptable by the next stage following the LNA in the receiver path.
A novel circuit structure of a common-gate single-stage LNA has been proposed in this work. The Ku-band LNA has been designed using the TSMC 0.18-µm CMOS process. New general analytical expressions have been derived for the noise factor of a LNA with a common-gate input stage. Earlier works have inherently assumed in their analysis a common-source input stage and derived the corresponding noise factor expressions from the power-constrained noise optimization analysis. We have used a similar approach in deriving the corresponding noise factor expressions for a common-gate input stage configuration. The simulation results for the design yield a minimum noise figure (NF) of 4.86 dB and a maximum S21 of 10.55 dB in the Ku-band. The circuit displays a high linearity with an IIP3 value equal to 12 dBm and P1-dB value equal to -3 dBm both of which are obtained at the mid-band frequency of 15-GHz. Detailed input and output matching networks have been designed to maintain a low NF and a high gain across the band. The LNA operates from a 1.8 V supply voltage and consumes a current of 5.56 mA excluding the output buffer. The total power consumption of the circuit including the output buffer is obtained as 19.44-mW from the design. After the design, the layout for the LNA circuit was completed using the Cadence Virtuoso tool and the EM simulation was done using the ADS Momentum RF tool. The fabricated chip was measured using the on-wafer chip measurement procedure and the corresponding measurement results obtained have been shown.

並列關鍵字

Broadband, Ku-band, LNA, Low-noise amplifier, RF IC, Wideband.

參考文獻

[1] B. Afshar, Ali M. Niknejad, “X/Ku Band CMOS LNA Design Techniques,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 389-392, Jun. 2006.

[3] B. Razavi, "Gadgets Gab at 60 GHz," IEEE Spectrum, Volume 45, Issue 2, pp. 46-58, Feb. 2008.

[4] Richard Chi-Hsi Li, "RF Circuit Design," John Wiley & Sons, 2009.

[6] R. M. Fano, "Theoretical limitations on the broadband matching of arbitrary impedances," J. Franklin Institute, vol. 249, pp. 57-83, Jan.-Feb. 1950.

[7] H. Zhang, X. Fan, E. Sánchez-Sinencio, "A Low-Power, Linearized, Ultra-Wideband LNA Design Technique," IEEE J. Solid-State Circuits, vol. 44, No. 2, Feb. 2009, pp. 320-330.