具寬頻操作之同步映射延遲電路

Wide Range Synchronous Mirror Delay

李昆樺(Kun-Hua Lee)

指導教授 ： 黃弘一

國立臺北大學/電機資訊學院/電機工程研究所/碩士(2010年)

摘要

在現在電路應用中，例如SDRAM是使用外部電路來改變記憶體內部的狀態。由於輸入緩衝器和輸出驅動器會造成內部訊號和外部訊號之間的時脈偏斜，因此若是想要增加記憶體的效能就必須消除此時脈偏斜。因此我們可以使用同步映射延遲電路來完成消除時脈偏斜，但是當系統的操作時脈越來越高，傳統的同步映射延遲電路在可操作頻率範圍有著許多限制，因此此論文提出藉由利用除頻器將訊號降頻，以及新式的取樣方法來增加整體操作頻率範圍。此測試晶片以台積電0.18um 1P6M製程實現，晶片面積為0.607×0.461 mm2，透過模擬的可操作頻率範圍可從240MHz到700MHz。

關鍵字

相位同步 ； 同步延遲 ； 同步映射延遲

並列摘要

Some applications, like SDRAM uses an external clock to change the internal state of the memory. The internal clock is a delayed signal of the external clock. The clock skew between the external clock and internal clock is the sum of the input buffer delay and the output driver delay. It can improve the memory performance by removing the clock skew between the external clock and the internal clock. That’s why we need synchronous mirror delay circuits. But the system operating clock is faster and faster recently. The conventional synchronous mirror delay circuits have some limitations to operate in a high input frequency. This thesis proposes a new way to increase the operating frequency range by adding a divider and a new sample method. The chip can be applied to the applications needing to synchronize higher frequency. Finally, the test chip is implemented by TSMC 0.18um 1P6M process and the chip area is 0.607×0.461 mm2. The operating frequency range of the simulation result is 240MHz to 700MHz.

並列關鍵字

Synchronous ； Delay ； SMD

參考文獻

[1] T. Saeki, Y. Nakaoka, M. Fujita, et al., “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1656-1665, Nov. 1996.

[2] T. Saeki, H. Nakamura, and J. Shimizu, “A 10 ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based on An Interleaved Synchronous Mirror Delay Scheme,” in Proc. IEEE Symp. VLSI Circuits, Dig. Tech. Paper, 1997 pp. 109-110.

[3] K. Sung, B. D. Yang, and L. S. Kim, “Low power clock generator based on area-reduced interleaved synchronous mirror delay,” in Proc. IEEE Int. Symp. Circuits and Syst., vol. 3, 2002, pp. 671-674.

[4] T. Saeki, K. Minami, H. Yoshida, and H. Suzuki, “A direct-skew- detect synchronous mirror delay for application-specific integrated circuits,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 372-379, Mar. 1999.

[5] C. H. Sun and S. I. Liu, “A Mixed-Mode Synchronous Mirror Delay Insensitive to Supply and Load Variations,” Journal of Analog Integrated Circuits and Signal Processing, vol. 39, pp. 75-80, Apr. 2004.