倍數延遲鎖定迴路之寬頻時脈產生器

傳統的倍頻延遲鎖定迴路(Multiplying Delay-Locked Loop, MDLL)使用循環式延遲線(Cyclic Delay Line)為主要電路架構，其鎖定行為需要一個外部重置信號，讓系統在開啟或改變外部倍頻數時，從最小延遲開始操作，否則系統總延遲將不會落在鎖定範圍內，造成迴路無法鎖定或諧波鎖定的情況產生。本論文第三章提出的倍頻延遲鎖定迴路，使用新設計的頻率偵測器與改良式的多工器選擇邏輯電路，再加上一個模態選擇電路來解決上述提到的問題並改進低頻輸出的時脈抖動表現。第四章提出另一個改良版本的倍頻延遲鎖定迴路，經由設計一個非常簡化的鎖定/頻率偵測器以取代第三章提出的頻率偵測器與鎖定偵測器，一個快速鎖定的寬頻時脈產生器得以完成，而且不需要任何外部重置信號。為了實現一個良好輸出表現的寬頻時脈產生器，使用新設計的可調整電流式電荷幫浦，能固定住延遲鎖定迴路的迴路頻寬以達成上述目標。我們使用互補式金氧半電晶體0.35μm的製程來實做晶片。本設計可以產生50~500MHz的輸出時脈，不需額外的重置電路即可將迴路鎖定在所需的輸出時脈頻率，並可避免諧波鎖定或無法鎖定的情況發生。由於此設計不需外部信號來重置系統初始總延遲，且可以任意改變倍頻數以切換操作頻率，故可以相容於一般鎖相迴路系統。

關鍵字

延遲鎖定迴路；循環式脈衝產生法；時脈產生器；鎖定範圍

並列摘要

The traditional multiplying delay locked loop(MDLL) uses cyclic delay line as its main architecture. The locking behavior needs an external reset signal to let the system start from minimal delay initially or when multiplication factor is required to change. The proposed MDLL in chapter 3 has a new frequency detector and mux control logic with added mode selection circuit to solve the problem above. Therefore, a wide range clock generator can be achieved with small peak-to-peak output jitter. Another modified version of MDLL is proposed in chapter 4 with a quite simplified lock/frequency detector to take the place of frequency detector and lock detector designed in chapter 3. Therefore, a fast-locking wide range clock generator is accomplished without any need of external reset signal. Additionally, to implement a wide range clock generator with very small output jitter, a new charge pump with adaptive supply current will be designed to fix the loop bandwidth of delay locked loop to achieve the target above. These chips are designed in 0.35um CMOS process. A wide range clock generator is proposed with frequency ranging from 50MHz to 500MHz. Any external reset signal is unnecessary to set the total delay of system minimal delay and the MDLL system is able to operate at appropriate frequency avoiding any harmonic locking or false condition. With arbitrarily multiplication factor to switch operation frequency to required one, the proposed architecture will be able to be integrated to any phase locked loop system easily.

並列關鍵字

Delay-Locked Loop ； Cyclic Pulse Generation ； Clock Generator ； Lock Range

參考文獻

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[7] Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle”, IEEE Journal of Solid-State Circuits, Volume 37, Issue 8, Aug. 2002 Page(s):1021 - 1027

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High Resolution Programmable Frequency Divider ,IEEE,2005.

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倍數延遲鎖定迴路之寬頻時脈產生器

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