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  • 學位論文

雙模同步切換式升壓轉換器之研製

Design and Implementation of a Dual-Mode Synchronous Boost Converter

指導教授 : 劉萬榮
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摘要


針對升壓轉換器在啟動時具有過大的切換電流,本論文設計兩階段軟啟動電路,能有效地抑制轉換器於啟動時,所產生過大的切換電流並且縮短啟動時間。主要工作原理為對輸出端電容提供一穩定電流進行初步的充電,於第二階段時,再輸入一脈衝寬度逐漸增加的切換訊號,使得輸出電壓逐漸升至預期的電壓準位。控制模式上採用電壓模式脈衝寬度調變與電流抑制式脈衝頻率調變,此兩種架構方式可透過模式選擇控制訊號,讓轉換器能依負載輕重選擇效率較高的操作模式,應用上脈衝寬度調變在負載電流為200mA時,轉換效率可高達96%,並且輸出電壓漣波小於16mV,而當轉換器處於輕負載工作下,可切換至脈衝頻率調變以改善脈衝寬度調變在輕負載工作時效率不佳的缺點,其負載電流在1mA時轉換效率可高達86%。 此升壓轉換器使用台灣積體電路公司0.35um 2P4M CMOS製程來實現,輸入工作電壓範圍為2.7∼4.2V,而輸出電壓為5V,最大輸出電流為200mA,其輸入電壓調節率最小為0.0048(V/V),而負載調節率最小為0.038(V/A),當轉換器在無負載情況下,最小靜態電流為38uA。

並列摘要


In this paper, a two-stage soft start circuit is designed to effectively suppress the heavy switch current during start-up of the boost converter. The two-stage soft start circuit can also help improve in reducing the start-up time. In the first stage, the presence of heavy current is suppressed to provide stable current on the output capacitor. In the second stage, the input signal on the switch gradually increases the duty cycle, which causes the output voltage to gradually rise up to the anticipated voltage level. The control models being utilized in this system are voltage mode PWM and current limit mode PFM. The Mode Selector Control Signal chooses which of the two structures need to be operated to obtain high efficiency converter depending on the load requirement. For PWM application under load current of 200mA, the conversion efficiency may reach as high as 94% with output voltage ripple smaller than 16mV. However, when the converter is under light load, the operation is change to PFM to improve the efficiency. During this operation the conversion efficiency may reach as high as 85% with load current at 1mA. This Dual-Mode Synchronous Boost Converter system is supported from Taiwan microcircuit company and is based from 0.35um 2P4M CMOS process. The operating input voltage range is between 2.7V to 4.2V with output voltage of 5V at maximum output current of 200mA. It has a line regulation of 0.0048(V/V) and a load regulation of 0.038(V/A). Furthermore, when the switch is operating in non-load condition, the minimum quiescent current is 38uA.

參考文獻


[42] B. Lee, "Technical review of low dropout voltage regulator operation and performance," Application Report, Texas Instruments Inc., literature number SLVA072.
[5] V. Mannama, R. Sabolotny, and V. Strik, "Ultra low noise low power LDO design," 2006, pp. 1-4.
[10] Y. Liu, P. Sen, and S. Huang, "Function control-a novel strategy to achieve improved performanceof the DC-to-DC switching regulators," IEEE Transactions on Industrial Electronics, vol. 42, pp. 186-191, 1995.
[15] S. Maniktala, Switching power supplies A to Z: Newnes, 2006.
[19] M. Mihaiu, "Toward the “ideal diode” using power MOSFET in full wave synchronous rectifiers for low voltage power supplies," 2008, pp. 1384-1387.

被引用紀錄


劉啟宇(2010)。以數位訊號控制器為控制核心實現功率因數校正級之設計〔碩士論文,國立臺北大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0023-1507201021392000
徐志杰(2011)。應用於電源供應器前級之數位控制功率因數校正器之設計〔碩士論文,國立臺北大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0023-0109201113463100

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