自我偏壓交叉耦合全差動運算放大器之分析與應用

Analysis of Self-Biased Cross-coupled Fully-Differential CMOS Operational Amplifier and Applications

張耀中(Yao-Chung Chang)

指導教授 ： 陳朝烈

崑山科技大學/工程學院/電子工程研究所/碩士(2005年)

摘要

現今的Mixed Signal SoC裡，往往都包含了數位以及類比的電路，而在這些電路裡面又以類比的電路所佔據的面積為最大，因為在類比電路中會包含主動(例如運算放大器)以及被動的元件(例如電阻電容)和一些效能的要求之下(例如高增益、高頻寬)，而必須增加額外設計電路，在現今的社會裡，隨著CMOS製程技術減少電晶體通道長度，爲了就是希望可以達到以最小的元件面積，期望可以以一個晶片的大小，把混合信號系統完整的做在晶片上，這不僅僅是技術成長更代表著如何減少成本來達到高效能的SoC。
在這篇論文中，提出了一個低成本全差動運算放大器，在這使用了一組自我偏壓架構的輸出級和具有高線性度的交叉耦合(Cross-coupled)輸入級。並且利用以上電路來提出一個自我偏壓的模型，在根據這個模型之下，可以讓設計者在不同的考量下來做設計與改變，另外也成功克服了偏壓電路所造成面積浪費並提升效能並且在我們這自我偏壓的架構下不用共模回授電路即可達到高共模拒斥比。基於這個理論，在其中一個實例中，我們進行了許多分析並和模擬結果進行比對，其結果吻合。晶片實現上，使用了TSMC 0.35mm的製程下，晶片面積為84´67mm2，由於不需要電流鏡、額外偏壓電路、以及補償電路，晶片面積僅目前最新文獻所載的十分之一，在負載100pF的情況下以儀器測量得的效能為DC gain 60dB, slew-rate 3 v/ms, 頻寬為 7.8Mhz, and總諧波失真為-48dB。
在應用方面，因為三角積分調變器在電壓模式中，大部分還是以運算放大器為主，所以在這我們把自我偏壓全差動交叉耦合運算放大器應用在三角積分調變器裡，並且成功改善了一般三角積分調變器大面積的問題，在透過自我偏壓模型的分析後，可以改善運算放大器的效能進而改善三角積分調變器的效能。

關鍵字

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並列摘要

Nowadays mixed signal SoCs most have several analog circuits, which occupies large chip area. In analog circuits, operational amplifiers are usually the primary cells comprising passive parts. These passive parts are used to achieve high gain, high frequency, stability, and some other performance issues. Under these performance requests, designers must increase extra design circuitry. In nowadays, though CMOS process has reduced transistor dimensions, downsizing chip area is still an important topic. Most studies pay much design effort in this downsizing to integrate mixed signal system with digital system. Therefore, downsizing will lead the technology grows in reducing the cost while increasing SoC efficiency.
In this thesis, we propose a low cost fully differential operational amplifier design method, which uses a novel self-biased cascode output stage and a high linearity cross-coupled input stage. We induce a general self-biased model for fully differential operational amplifiers in this thesis. In fact, according to this model, users can change their design at will with different considerations. Furthermore, the self-biased model achieves high common-mode rejectsion ration (CMRR) without common mode feedback (CMFB) circuit and it avoids extra biasing circuits. Consequently, this dramatically reduces the area wasting and achieves high performance.

We apply the proposed model in a successful OpAmp design. In this example, we have made comparisons among a lot of analyses and experiments. We find that the analysis results and the experimental results are matched. Because we do not need the current mirrors, extra bias circuit, neither compensating circuit, the chip is fabricated within only a 84´67mm2 area by using TSMC 0.35μm standard CMOS technology. The chip area is only about 1/10 of the state-of-art OpAmps. Loaded with more than 100pF capacitance, the OpAmp possesses 60dB DC gain, 3v/μs slew-rate, 7.8Mhz unity-gain bandwidth, and -48dB THD.
Because most voltage mode sigma delta modulator uses OpAmp as kernel element, we apply our OpAmp to complete the first-order sigma delta modulator. After applying our OpAmp in sigma delta modulator, we have successfully improved large dimension problem in the sigma delta modulator design. In the future, we can effectively improve the sigma-delta modulator performance by the analyses of the self-biased model

並列關鍵字

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參考文獻

[1] Michael S. Kappes, ”A 2.2-mW CMOS Bandpass Continuous-Time Multibit D–S ADC With 68 dB of Dynamic Range and 1-MHz Bandwidth for Wireless Aplications,”IEEE Journal of Solid-State Circuits, Vol. 38, August 2003, pp. 1098-1104.

[3] S. Mehrmanesh, H.A. Aslanzadeh, M.B. Vahidfar, M. Atarodi, ”A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters,” International Symposium on Circuits and Systems, Vol. 1, May 2003, pp. 273-276

[4] G. A. Rincon-Mora, R. Stair, “A Low Voltage, Rail-to-Rail, Class AB CMOS Amplifier With High Drive and Low Output Impedance Characteristics,” IEEE Transactions Circuits and Systems II, vol. 48, August 2001, pp. 753-761.

[5] P. Bruschi, D. Navarrini, M. Piotto, ”A High Current Drive CMOS Output Stage With a Tunable Quiescent Current Limiting Circuit,” IEEE Journal of Solid-State Circuits, vol. 38, August 2003, pp. 1416-1420.

[6] R. E. Vallee, E. I. EI-Masry, “A Very High-Frequency CMOS Complementary Folded Cascode Amplifier,” IEEE Journal of Solid-State Circuits, vol. 29, February 1994, pp. 130-133.