透過您的圖書館登入
IP:3.138.101.1
  • 學位論文

高精度寬範圍之頻率與工作週期共測儀之設計

FPGA-based Precision Frequency/Duty Cycle Co-Measurement System Design

指導教授 : 蔡國瑞
共同指導教授 : 林明權
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


本文提出利用FPGA設計出一種超精密度、寬量測範圍、以及自動換檔的輸入信號頻率量測與工作週期之同步量測技術。 在頻率量測方面,在100MHz的參考信號頻率下,精密度高達10ns,其量測頻率可以低於次赫次(sub-Hz)以下。可量測之最高頻率,使用Spartan3系列FPGA可達到200MHz以上,Virtex4-5 FPGA可達到400MHz以上。至於工作週期的同步量測,其解析度高達0.0000001%。 本量測技術,係以模組化設計,每一種量測演算技術都是個獨立的IP設計,可提供給其他的應用系統使用。

關鍵字

FPGA 計頻器 工作週期

並列摘要


This paper proposes to use FPGA to design a super-precision, wide measurement range And Automatically convert the input signal frequency and duty cycle measurement of simultaneous measurement technique. In the frequency measurement can be divided into High-frequency and low frequency measurement About high-frequency measurement is used reciprocal counting Frequency Measurement, And Low-frequency measurement is the measurement method by measuring cycle. Frequency measurements in the 100MHz frequency stable reference signal. Stable reference frequency to 100MHz frequency measurement. Precision will reach 10ns. The measurement frequency can be lower than the sub-Hz. Reference frequency can change the highest frequency of measurement. If you use Spartan3 FPGA can achieve more than 200MHz or Virtex4-5 FPGA can reach more than 400MHz. Duty cycle synchronization algorithm using statistical measures. Reference frequency of 100MHz for resolution to 0.0000001%. About High-frequency duty-cycle of the random number generator used to reduce the error.

並列關鍵字

FPGA Frequency Counters Duty Cycle

參考文獻


[2] Guo-Ruey Tsai, Min-chuan Lin (2006), ” FPGA-based re-configurable measurement instruments with functionality defined by user”, EURASIP Journal on applied Signal Processing, Volume 2006, Article ID 84340, Pages 1–14.
[5] S. A. Dyer, Survey of Instrumentation and Measurement, John Wiley & Sons, NY, 2001.
[1] 蔡國瑞, 林明權, ”可重組態之電子實驗儀器平台”, 中華民國發明專利(2009/7/24初審核准),2009.
[3] Guo-Ruey Tsai, Min-Chuan Lin, Wen-Zong Tung, Kai-Chu Chuang, Sung-Yu Chan, (2003), “Wide-Band and Precisely Measurement method of Phase Detector Based on FPGA with Embedded Processor”, 2003 International conference on Informatics, Cybernetics and Systems, I-Shou, ROC., pp102-106.
[4] Min-Chuan Lin, Guo-Ruey Tsai, Chun-Yi Liu, Shi-Shien Chu, (2006), “FPGA-Based High Area Efficient Time-To-Digital IP Design”, Proceedings IEEE TENCON2006, 14-17 Nov. 2006, Hong Kong.

被引用紀錄


杜昱函(2011)。以FPGA晶片實現智慧型電子控制系統設計〔碩士論文,崑山科技大學〕。華藝線上圖書館。https://doi.org/10.6828/KSU.2011.00015
沈俊佑(2010)。智慧型LED照明控制系統設計〔碩士論文,崑山科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0025-2807201011465200

延伸閱讀