HDL形式之IP模組的浮水印保護法

Watermarking HDL Codes for Soft IP Protection

吳俊融(Chun-Rong Wu)

指導教授 ： 林明權

崑山科技大學/工程學院/電子工程研究所/碩士(2008年)

摘要

一般SoC系統的設計，常利用軟體HDL程式碼形式，組成許多的可再使用(reuse)的元件，但因為這些可再使用元件的HDL封裝方式，使得智慧財產權，往往很難加以保護的。
本文提出一簡易的浮水印加密保護法來規劃HDL程式碼的智慧財產權；對於組合邏輯電路，以LUT(ROM-based)取代一般的VHDL程式語法，對於序向邏輯電路，以RAM-based的FSM來設計，並將個人規劃的浮水印標記，嵌入LUT(ROM-based)或是RAM-based的FSM狀態記憶體內。
本文提出一些Opencore設計的HDL程式，套上本論文所提出的簡易浮水印加密保護法，證實經過浮水印加密的程式，再以FPGA合成、實現後，完全符合原Opencore設計的功能，並且只增加少許晶片系統的資源，因此頗適用於HDL可再使用程式模組的智慧財產權保護。

關鍵字

浮水印加密 ； 可再使用 ； 智慧財產權保護

並列摘要

Reuse-based Intellectual property (IP) design is one of the most promising techniques to take the SoC design quickly into market. However, soft IPs has higher protection requirements than hard IPs and most existing IP protection techniques are not applicable to soft IPs. In this paper, we proposed two practical schemes for HDL code protection by hiding author’s signature which is also called as watermark and similar to the idea for hard IP and multimedia data protection.
We proposed how to embed watermark into HDL source codes by LUT (ROM) units and distributed SRAM. For combinational logic system, the LUT (ROM) components are very suitable for hiding watermarking. For sequential logic system, we use RAM-based FSM technique to embed the personal watermarking messages.
We have modified some opencore design module with our watermarking technique, and have proved that without changing the original algorithm in the reused device and increasing additional HDL modules, the proposed watermarking technique is suitable for HDL-based reused IP.

並列關鍵字

LUT ； FSM

參考文獻

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