本文提出利用FPGA之可重組態(re-configurable)、內嵌Block RAM、以及內嵌式微處理控制器之特性,設計出一個基於FIFO技術的串流視訊加速器,並且包裝此視訊信號加速器IP,成為一般SOC系統軟體控制形式之串流視訊co-processor的影像加速處理與應用IP。 本文製作完成一個獨立之即時串流影像之擷取、處理、縮小、與VGA顯示模組的技術,並且應用於即時保全監控影像顯示系統上。本系統可同時提供4組以上之類比攝影機視訊的信號輸入與處理,且每一個影像視訊均可達30fps以上,在4組類比攝影機輸入的運作下,只消耗Xilinx ML401實驗板XC4VLX25-FF668-10C晶片不到30%之系統資源。
This article takes advantages of re-configurability, built in block RAM and embedded processor from a FPGA chip, to design a FIFO_based stream video signal procession accelerator IP. The accelerator IP can be packed into a general propose stream video co-processor which is used in SOC-based video signal procession application in form of software control. This work presents an independent real-time platform for retrieval, processing, scaling and VGA display of stream video signal, which can be utilized in real-time surveillance system image display. This platform simultaneously provides four sets of analog camcorder video inputs and processing. The image refreshing rate is above 30 frames per second. Operated under four analog camcorders, the platform IP only occupies 30% system hardware resources.