可調式環式振盪器及輸出緩衝器設計

Design of Tunable Ring Oscillator and Output Buffer

曾世緯(Shih-Wei Tseng)

指導教授 ： 劉偉行

國立虎尾科技大學/電機資訊學院/光電與材料科技研究所/碩士(2010年)

https://doi.org/10.6827/NFU.2010.00011

摘要

本論文提出一種利用數位控制碼改變訊號傳輸路徑之環式振盪器，經由路徑的改變，振盪器可產生不同的輸出頻率，並在最後一級利用可調整電流之反相器進一步做頻率的調整。相較於一般傳統環式振盪器，本電路可以擁有更多的輸出頻率。

本數位控制碼改變訊號傳輸路徑之環式振盪器經由HSPICE模擬，在TSMC 0.35μm mixed-signal 2P4M polycide 3.3/5V製程參數下，可有32種不同的輸出頻率，其中最大振盪頻率為1.05GHz，最小振盪頻率為188.4MHz，且在供應電壓3.3V，負載電容為20pF時，最大消耗功率為402.52mW

由於振盪器可產生不同之輸出頻率，輸出振盪頻率較低時所使用緩衝器的級數較少，反之輸出振盪頻率較高時所使用緩衝器級數較多。若振盪頻率較低時及振盪頻率較高時使用相同級數之緩衝器將會造成額外的功率消耗，因此本論文提出一種可調整緩衝器級數之串級緩衝器，藉由調整緩衝器之級數，使得輸出振盪頻率為低頻時，使用較少級數之緩衝器，以避免額外的功率消耗。當輸入訊號之頻率範圍是1MHz∼100MHz時，本論文提出之串級緩衝器的級數可依照輸入訊號之頻率由1級增加至3級。

本論文提出之電路在使用TSMC 0.35μm mixed-signal 2P4M polycide 3.3/5V的製程參數下進行佈局，佈局後經由HSPICE電路模擬軟體進行模擬，當供應電壓為3.3V，負載電容為15pF，輸入訊號分別是1MHz與10MHz時，使用本論文提出之可調整緩衝器級數之串級緩衝器，其功率消耗較傳統固定級數之串級緩衝器，可分別減少110.22mW與105.93mW。

關鍵字

關鍵字 ； 振盪器 ； 數位碼 ； 反相器 ； 緩衝器

並列摘要

A ring oscillator, which uses digital codes to control the transmission paths, has been proposed in this thesis. As the transmission paths changes, different output frequencies are generated. Moreover, a current-adjusted inverter is used as the last output stage. Therefore the output frequency can be further calibrated. Comparing to the conventional oscillators, the proposed one can have multiple output frequencies.

The proposed digital-code-controlled ring oscillator has been simulated with HSpice where 0.35μm mixed-signal 2P4M polycide 3.3/5V fabricated parameters have been adopted. Simulation results show that, 32 different output frequencies can be obtained. The maximum frequency is 1.05GHz and the minimum frequency is 188.4MHz. As the supply voltage is 3.3 V and the load capacitance is 20 pF, the maximum power consumption is 402.52 mW.

Since the oscillator can generate different output frequencies, the low output frequency needs less number of stages of cascaded buffers while the high output frequency needs more. If both the low output frequency and the high output frequency use same stages of cascaded buffers, it will bring extra power consumptions at low output frequency. In this thesis, an adaptive stage cascaded buffer has been proposed. In order to reduce additional power dissipation, the stages of cascaded buffers will be adjusted according to the output frequency. In the proposed circuit, as the input signal frequency varies from 1MHz to 100MHz, the corresponding stage of output buffer can be increased from 1 to 3.

The proposed adaptive cascaded buffer has been simulated with HSpice where 0.35μm mixed-signal 2P4M polycide 3.3/5V fabricated parameters have been adopted. As the supply voltage is 3.3V, load capacitance is 15pF, and the input signal frequency is from 1MHz to 100MHz. The post-layout simulation results show that, the power consumption of the proposed circuit can reduce 110.22mW and 105.93mW, respectively, as compared to the conventional buffer.

並列關鍵字

Keyword ； oscillator ； digital code ； inverter ； buffer.

參考文獻

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[2] Straayer, M. Z. and Perrott, M. H., “A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 4, pp. 1089 – 1098, April 2009.

[4] Hung Tien Bui, “Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis,” 2008 IEEE International Symposium on Circuits and Systems, pp. 3422 – 3425, 18-21 May 2008.

[5] Milicevic, S.; MacEachern, L. and Mahmoud, S., “Frequency of oscillation for a multi-band voltage controlled ring oscillator,” 2007 IEEE Northeast Workshop on Circuits and Systems, pp. 486 – 489, 5-8 Aug. 2007.

[6] Ghani, A.A.A.and Saparon, A., “A 1.4GHz CMOS Low-Phase Noise Voltage-Controlled Ring Oscillator,” 2007 5th Student Conference on Research and Development, pp. 1 – 5, 12-11 Dec. 2007.