光電鎖相放大器之類比互補式金氧半積體電路設計

Analog CMOS integrated circuit implementation of the photonic lock-in amplifier

童政碩(Zheng-Shuo Tong)

國立虎尾科技大學/電機資訊學院/光電與材料科技研究所/碩士(2006年)

摘要

本論文提出一個以兩級運算放大器為基本元件之光電鎖相放大器之設計， 利用此運算放大器來完成雙輸出運算放大器、四象限類比乘法器(four-quadrant analog multiplier)、平方根和電路、絕對值電路與除法器，參數係採用TSMC 0.35微米之製程，此運算放大器具有80 dB的開迴路增益，乘法器有± 0.4 V的線 性輸出，而平方根和電路可完成兩訊號平方和開根號之功能，將這些元件的組 合來完成鎖相放大器， 光電鎖相放大器最主要利用相位靈敏檢測技術（Phase- Sensitive Detection，PSD），它是由特定頻率與相位的參考訊號與相同頻率之 待測輸入訊號做相乘運算所得之結果，再藉由低通濾波器過濾其雜訊得到直流 輸出值，最後將此直流輸出做規一化(normalization)，即是我們要的輸出結果。 模擬結果顯示本晶片可量測輸入訊號1 μV~50 μV，量測頻率50 Hz~1 kHz之 間，光偵測器也將整合於同一晶片上，晶片的總消耗功率約為66 mW。

並列摘要

In this thesis, we propose the analog CMOS integrated circuit
implement of a Lock-in amplifier. This design is based on a two-stage
operational amplifier (OPA). A dual-output OP amplifier, a four-quadrant
analog multiplier, a square-root circuit, a modulus circuit, and a division circuit are all based on this OPA. The design parameters are based on the TSMC 0.35 μm process. The OPA has an open-loop gain of 80 dB and the multiplier has a linear output range of ± 0.4 V. The key technique applied in Lock-in amplifier is the Phase-Sensitive Detection (PSD), which pick the signal with the specific frequency and phase by multiply the input signal with a reference signal. The result signal is then filtered by a low pass filter to obtain a DC value. Finally, the output voltage value is normalized to overcome the light intensity variation problem. The test input signal voltage is about 1 μV~50 μV and the bandwidth is about 50 Hz~1 kHz. A photo detector is also fabricated on the identical chip .The total power consumption is about 66 mW.

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