互補式金氧半導體射頻除頻器與倍頻器之注入鎖定機制分析與設計

Design and Analysis of Injection Lock in CMOS Radio Frequency Divider and Multiplier

林子弘(Tzu-Hung Lin)

指導教授 ： 吳建華

國立中正大學/工學院/電機工程學系/碩士(2013年)

摘要

本論文主要研究方向為：射頻收發機中，頻率合成器所需之注入鎖定除頻器與倍頻器；並使用台積電1P6M 0.18μm CMOS製程設計。本論文使用不同電路機制增強注入電流強度以提升鎖頻範圍。
本論文提出二個除頻器分別為除三電路及除四電路並提出一三倍頻器。與已發表之多重注入除頻器比較，本論文提出之注入鎖定除頻器，採用更簡單的架構提升注入效率，並不增加額外的功率消耗。由鎖頻公式知，電路之輸出功率越高，鎖頻範圍越難增加。本論文提出混頻式注入鎖定三倍頻器；目的在達成高輸出功率時，亦保持適當的鎖頻範圍。
第二章之除三除頻器結合直接注入除三除頻器與直接注入除二除頻器，並將交叉耦合對共源極節點之偶倍頻訊號回授，達到提高鎖頻範圍的目的。鎖頻範圍由11.2 GHz至18.1 GHz。偏壓為1.2V，功率消耗為2.69mW。第三章之除四除頻器取代傳統非線性放大器產生所需三倍頻的機制，本論文將其交叉耦合對共源極節點之偶倍頻訊號與震盪器的基頻訊號混頻得到除四除頻器所需的三倍頻訊號，以此機制提升注入電流強度，進而達到高鎖頻範圍的目的。鎖頻範圍由20.8 GHz至27.6 GHz。偏壓為1V，功率消耗為3.68mW。第四章之乘三倍頻器取代傳統非線性放大器，採用雙推式振盪器之偶倍頻訊號與注入之基頻訊號混頻得到三倍頻訊號，將此三倍頻訊號注入至震盪腔完成注入鎖定機制，在高輸出功率的同時，維持足夠的鎖頻範圍。鎖頻範圍由6.88 GHz至9.12 GHz。偏壓為1V，功率消耗為4.2mW。
經模擬與量測證實，本論文提出之除頻機制能有效提升鎖頻範圍。未來的進階研究，可朝增強注入電晶體之混頻效率繼續研究。

關鍵字

注入鎖定 ； 三倍頻器 ； 除四電路 ； 除三電路 ； 倍頻電路 ； 除頻電路

並列摘要

The study of this thesis focuses on the design of injection-locked frequency divider and multiplier used in the phase lock loop of the wireless transceiver. All the proposed circuits are implemented by TSMC 0.18μm 1P6M CMOS process.
In this thesis, two wide locking range frequency dividers and one injection-locked frequency tripler is proposed. Based on the locking range formula, the strength enhancement of injection signal will make locking range wider. Following this concept, this thesis demonstrates new methods to intensify the strength of injection signal.
Compared to the published injection-locked frequency dividers, the injection-locked frequency dividers proposed in this thesis demonstrate simple and efficient method to enhance the injection strength with low power consumption. The locking range formula shows that it is difficult to maintain locking range with high output power. Therefore, the proposed ILFT demonstrates a new method achieving high output power with suitable locking range.
In chapter II, a low power consumption and wide locking range injection-locked frequency divider by three is realized. This proposed ILFD combines a direct injection-locked frequency divider by three and direct injection-locked frequency divider to achieve the divide-by-three mechanism. Furthermore, the even harmonic signal at the common source node of cross coupled pair is feedback to direct injection transistors. The injection current is enhanced with proposed structure. The measured locking range is from 11.2 GHz to 18.1 GHz (47.1%) with an injection power of 0dBm. The measured maximum output power is -3.1dBm with a tuning voltage of 2V. The power consumption of the core circuit takes 2.69mW from a 1.2V power supply.
In chapter III, a new method to produce the necessary third harmonic is demonstrated. The even harmonic signal at common source node of cross coupled pair is mixed with fundamental signal to generate the necessary third harmonic in divide-by-four frequency divider design. The measured locking range is from 20.8 GHz to 27.6 GHz (28.1%) with an injection power of 0dBm. The measured maximum output power is -0.4dBm with a tuning voltage of 2V. The power consumption of the core circuit takes 3.68mW from a 1 V power supply.
In chapter IV, a injection-locked frequency tripler by using mixing technique is demonstrated. This proposed ILFT uses a push-push oscillator to generate the even harmonic signal which is mixed with input signal. The conventional non-linear amplifier topology is replaced. The measured locking range is from 6.88 GHz to 9.12 GHz (28%) with an injection power of 0dBm. The measured maximum output power is -4.3dBm with a tuning voltage of 0V. The power consumption of the core circuit takes 4.2mW from a 1V power supply.
The simulation and measurement results proof that the division mechanism proposed in this thesis effectively enhance the locking range. In the future, it is a good extension to study how to intensify the mixing mechanism of injector.

並列關鍵字

Tripler ； Frequency Multiplier ； Frequency Divider ； Injection-Locked

參考文獻

[1] Ken Yamamoto, Minoru Fujishima, "A 44 μm 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range," IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 671–677, Mar. 2005.

[2] Ullas Singh, Michael M. Green, "High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz," IEEE J. Solid-State Circuits, vol.40, no.8, pp.1658-1661, Aug. 2005.

[3] R. L. Miller, "Fractional-Frequency Generators Utilizing Regenerative Modulation," Proc. Inst. Radio Eng., vol. 27, pp. 446–457, Jul. 1939.

[4] Hamid R. Rategh, Thomas H. Lee, "Superharmonic injection-locked frequency dividers," IEEE J. Solid-State Circuits, vol.34, no.6, pp.813-821, Jun 1999.

[5] Hui Wu, Lin Zhang, "A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3 Injection-Locked Frequency Divider," IEEE J. Solid-State Circuits, vol., no., pp.2482-2491, Feb. 2006.