互補式金氧半導體之注入鎖定式射頻振盪器設計

Design of CMOS Radio Frequency Injection Locked Oscillator

陳常鈞(Chang-Chun Chen)

指導教授 ： 吳建華

國立中正大學/工學院/電機工程學系/碩士(2012年)

摘要

本論文主要研究方向為：射頻收發機中，頻率合成器所需之注入鎖定振盪器；並使用台積電1P6M 0.18μm CMOS製程設計。為了提升鎖頻範圍，本論文的除頻器與倍頻器採用多重注入架構。

本論文提出二個應用在Ku頻段的除頻器與一個應用在K頻段的三倍頻器。與已發表之多重注入除頻器比較，本論文提出之多重注入除頻器，採用更簡單的架構提升注入效率，並保有更低的功率消耗。由鎖頻公式知，電路之輸出功率越高，鎖頻範圍越難增加。因此，本論文提出雙重注入三倍頻器；在達成高輸出功率時，亦保持適當的鎖頻範圍。

第二章之除二除頻器採三注入方式，結合直接注入與尾端注入除頻器，達到低功耗高鎖頻範圍的目的。鎖頻範圍由10.18 GHz至15.49 GHz。偏壓為1.2V，功率消耗為2.71mW。第三章之除三除頻器採雙注入方式，結合直接注入除三與直接注入除二除頻器，達到高鎖頻範圍的目的。鎖頻範圍由11.77 GHz至16.64 GHz。偏壓為1.2V，功率消耗為4.2mW。第四章之乘三倍頻器採雙注入方式，結合尾端注入與側邊注入非線性放大器，在高輸出功率的同時，維持足夠的鎖頻範圍。鎖頻範圍由21.38 GHz至23.37 GHz。偏壓為1.8V，功率消耗為9.22mW。

經模擬與量測證實，本論文提出之多重注入架構能有效提升鎖頻範圍。未來的進階研究，可朝超低偏壓之注入鎖定振盪器繼續研究。

關鍵字

注入鎖定式振盪器 ； 三倍頻器 ； 倍頻電路 ； 除頻電路 ； 多重注入

並列摘要

The study of this thesis focuses on the design of injection-locked oscillator which used in the phase lock loop of the wireless transceiver. All the proposed circuits are implemented by TSMC 0.18μm 1P6M CMOS process.

In this thesis, two wide locking range frequency dividers are demonstrated for Ku-band application and one injection-locked frequency tripler is demonstrated for K-band application. Based on the formula of locking range, the strength enhancement of injection signal will make locking range wider. Following this concept, this thesis demonstrates multi-injection injection-locked frequency oscillator. The multi signal injection paths effectively enhance the injection strength.

Compared to the injection-locked frequency dividers which had used multi-injection topology, the injection-locked frequency dividers proposed in this thesis demonstrate simple and efficient method to enhance the injection strength with low power consumption. The formula of locking range shows that it is difficult to maintain locking range with high output power. Therefore, the proposed ILFT demonstrates dual-injection topology achieving high output power with suitable locking range.

In chapter 2, a low power consumption and wide locking range triple-injection-locked frequency divider by two is demonstrated. This proposed ILFD with a way of triple-injection topology which combines two features of direct and tail injection frequency divider to enhance locking range. The measured locking range is from 10.18 GHz to 15.49 GHz (41.37%) with an injection power of 0dBm. The measured maximum output power is -3.42dBm with a tuning voltage of 2V. The power consumption of the core circuit takes 2.71mW from a 1.2V power supply.

In chapter 3, a dual direct injection-locked frequency divider by three with wide locking range is demonstrated. This proposed ILFD uses dual direct-injection technique which combines two features of direct injection paths to enhance locking range. The measured locking range is from 11.77 GHz to 16.64 GHz (34.28%) with an injection power of 0dBm. The measured maximum output power is -7.25dBm with a tuning voltage of 2V. The power consumption of the core circuit takes 4.2mW from a 1.2V power supply.

In chapter 4, a dual injection sub-harmonic injection-locked frequency tripler is demonstrated. This proposed ILFT combines tail nonlinear amplifier pairs and side nonlinear amplifier pairs to maintain locking range with high output power. The measured locking range is from 21.38 GHz to 23.37 GHz (8.89%) with an injection power of 0dBm. The measured maximum output power is -2.88dBm with a tuning voltage of 1.5V. The power consumption of the core circuit takes 9.22mW from a 1.8V power supply.

The simulation and measurement results proof that the multi-injection topology proposed in this thesis effectively enhance the locking range. In the future, it is a good extension to study the ultra low power supply injection-locked oscillator.

並列關鍵字

Tripler ； Frequency Multiplier ； Frequency Divider ； Multi Injection ； Injection-Locked Oscillator

參考文獻

[1] Ken Yamamoto, Minoru Fujishima, "A 44 μm 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range," IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 671–677, Mar. 2005.

[2] Ullas Singh, Michael M. Green, "High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz," IEEE J. Solid-State Circuits, vol.40, no.8, pp.1658-1661, Aug. 2005.

[3] R. L. Miller, "Fractional-Frequency Generators Utilizing Regenerative Modulation," Proc. Inst. Radio Eng., vol. 27, pp. 446–457, Jul. 1939.

[4] Hamid R. Rategh, Thomas H. Lee, "Superharmonic injection-locked frequency dividers," IEEE J. Solid-State Circuits, vol.34, no.6, pp.813-821, Jun 1999.

[5] Behzad Razavi, "A study of injection locking and pulling in oscillators," IEEE J. Solid-State Circuits, vol.39, no.9, pp. 1415- 1424, Sept. 2004.