互補式金氧半導體功率放大器線性器及分布式主動轉換器之研製

Design and Analysis of CMOS Power Amplifier Linearizer and Distributed Active Transformer

任勇年(Yung-Nien Jen)

指導教授 ： 黃天偉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.01641

摘要

隨著無線通訊技術的快速發展，為了有更高資料傳輸速率，射頻積體電路正朝向更高頻率、更廣頻寬之趨勢發展。毫米波功率放大器對於高頻系統應用來說，是重要且仍為瓶頸的。傳統上，高功率高效率功率放大器多是採用III-V族複合式微波單晶片製程。例如:砷化鎵(GaAs)及磷化銦(InP)高電子移動率電晶體(HEMT)製程。然而，互補式金氧半導體(CMOS)製程有著小尺寸、低成本、低功率消耗及高度整合性的優點，很適於毫米波應用。
在本論文中，討論了三個互補式金氧半導體(CMOS)功率放大器;其中包含一個設計在24-GHz及另外兩個設計在60-GHz.第一個功率放大器是實做在標準0.18微米互補式金氧半導體製程。將兩個疊接放大器串接，此功率放大器在22GHz時可達到15-dB小訊號增益、10.7% 的功率輔助效率以及16.8-dBm的輸出飽和功率。此電路同時實現了一個偏壓補償線性器去提升輸出1-dB壓縮功率(OP1dB)值。我們提升了2.8dB的輸出1-dB壓縮功率(OP1dB)值，當線性器偏壓在打開的狀態時。
第二及第三個電路是兩個V-頻帶分佈式主動轉換器(DAT)功率放大器分別使用90-奈米及130-奈米製程實現。90-奈米分佈式主動轉換器(DAT)功率放大器可達到四元件功率加成結果。此功率放大器展現了26±1dB高且平坦的小訊號增益從57-69GHz。且在60GHz達到18-dBm及14.5-dBm輸出飽和功率及12.2%和10.2%的功率輔助效率分別在3V及2V的供給電壓下。就目前來說，在60GHz的發表文獻中，此功率放大器展現了最高的輸出功率。
130-奈米分佈式主動轉換器(DAT)功率放大器亦可達到四元件功率加成結果。此功率放大器展現了峰值17.5(21)dB增益在57GHz，6.36(8.92) dBm的輸出1-dB壓縮功率(OP1dB)值，11.1(14) dBm的輸出飽和功率及5(6.2) %的功率輔助效率在2(3) V的供給電壓下。此電路與其他的商用標準130-奈米製程V-頻段功率放大器相比，有著最高的輸出1-dB壓縮功率(OP1dB)值，最高的輸出飽和功率值及緊密的晶片面積。

關鍵字

功率放大器 ； 互補式金氧半導體 ； 線性器 ； 分佈式主動轉換器

並列摘要

With the rapid development of wireless communication technologies, RF integrated circuits move toward higher frequencies, and wider bandwidth for high data transferring rate. The MMW power amplifiers (PAs) are important and remaining the bottleneck for high-frequency system applications. Traditionally, high-power high-efficiency PAs were mostly fabricated using III-V compound semiconductor MMIC processes, for instance, GaAs and InP HEMT processes. However, CMOS technology which has the advantages of small size, low cost, low power consumption, and high level of integration are appealing for MMW applications.
In this thesis, three CMOS power amplifiers including one designed at 24-GHz and two designed at 60GHz were discussed. The first PA is implemented in a standard 0.18-μm CMOS technology. By cascading two cascode stages, the power amplifier achieves 15-dB small signal gain, 10.7% PAE, and 16.8-dBm output saturation power at 22GHz. We also implement a bias compensation linearizer in order to improve OP1dB. After biasing the linearizer at on-state, the circuit can achieve 2.8dB improvement of OP1dB.
The second and third circuits are V-band DAT PA using 90nm and 130nm CMOS processes, respectively. The 90nm CMOS DAT PA performs 4-element combination. This PA performs a high and flat small signal gain of 26 ± 1 dB from 57 to 69 GHz. This PA delivers 18-dBm and 14.5-dBm output saturation power with 12.2% and 10.2% PAE under 3-V and 2-V supply, respectively at 60 GHz. To the best of our knowledge, this PA demonstrates the highest output power among the reported 60-GHz CMOS PAs to date.
The 130nm CMOS DAT PA also achieves 4-element combination. This PA demonstrates a peak gain of 17.5 (21) dB at 57GHz, OP1dB of 6.36(8.92) dBm, Psat of 11.1(14) dBm, and PAE of 5(6.2) % under 2(3) V supply voltage. The PA outperforms all the reported commercial standard CMOS V-band amplifiers in 130nm CMOS, highest output P1dB, and highest Psat as well as a compact chip size.

並列關鍵字

power amplifier ； CMOS ； linearizer ； distributed active transformer

參考文獻

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