利用數位減法器設計數位比較器

Design of Digital Subtractor Based Digital Comparators

辛政諺(Jheng-Yan Sin)

指導教授 ： 劉偉行

國立虎尾科技大學/電機資訊學院/光電與材料科技研究所/碩士(2011年)

摘要

本論文中提出數種全新的以CMOS設計之可擴充數位比較器。所提出的數位比較器適用於兩個8位元二進位數字比較，可比較出大於、等於，以及小於的關係。
第一個比較器為使用一位元減法器加上擴充模組實現的8位元數位比較器；第二個比較器使用四位元減法器，加上相關輸入端的邏輯判斷電路所組合而成；第三個比較器亦為使用四位元減法器電路所組合實現；但是與第二個比較器不同之處為，其中之四位元減法器架構不同，並且在輸入端加上控制開關；最後一個比較器亦為使用四位元減法器，然而與第三個比較器不同之處是在輸入端移除控制開關，此設計之用意是避免電路在切換時所產生的高阻抗狀態，以確保電路輸出的正確性。
本論文所提出之數位比較器經由HSpice軟體模擬，模擬結果顯示，當供應電壓為3.3V時，電路之操作頻率可達20MHz。

關鍵字

數位比較器 ； 模組化 ； 可擴充式

並列摘要

Several new CMOS module-based expandable digital comparators have been developed in the thesis. The proposed digital comparator can be used to perform the comparison between two multiple-bit binary numbers, and decide which one is equal, greater, or less than the other one.
The first proposed comparator was implemented by using 1-bit subtractor and related expanding modules. The second proposed comparator was composed of 4-bit subtractor and with some necessary determining logic circuits on their inputs. The third proposed one also use 4-bit subtractor as core circuits; however, the architecture of the 4-bit subtractor is different and a switch is added on the input of the circuit. The last proposed one also uses 4-bit subtractor as core circuits; however, the switches on the inputs were removed. Such design is intended to avoid the circuit being at the high-impedance state which will ensure the accuracy of the circuit.
All the proposed circuits have been simulated with HSpice. As the supply voltage is 3.3V, simulation results show that the related circuits are functional with 20MHz input signal.

並列關鍵字

digital comparator ； module-base ； expandable

參考文獻

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