1.8伏特十位元混合式類比數位轉換器的設計與製作

在許多的應用領域中，大都使用數位信號處理的技術來處理所傳輸的資料，因此在類比訊號源與數位信號處理系統之間，就必需存在一個將類比訊號轉換成數位訊號的介面電路，所以類比數位轉換器是目前混合訊號積體電路設計中，非常重要的一個部份。在各種類型的類比數位轉換器中，雙斜率式類比數位轉換器一般被使用於低轉換速率與高精確度的相關儀表應用中，至於連續逼近式類比數位轉換器則在功率消耗與轉換速度方面有較佳的優勢。本論文將結合連續逼近式架構與雙斜率式架構，設計與製作一個混合式的類比數位轉換器，在高位元的部份將採用連續逼近式架構，結合雙取樣技術；至於低位元的部份使用雙斜率式架構，並以開關電容式積分器進行設計。在本論文中，連續逼近式類比數位轉換器包含取樣保持電路、數位類比轉換電路、比較器與連續逼近暫存器；雙斜率式類比數位轉換器包含米勒取樣保持電路、開關電容式積分器、比較器與計數器。本研究使用TSMC 018um 1P6M的製程進行設計與製作，實現一個電源電壓1.8伏特，取樣頻率為5KS/s的十位元混合式類比數位轉換器。當輸入訊號為92.7Hz時，經由佈局後模擬可得到SFDR與SNDR分別為51.2dB與50.1dB、有效位元數為8.03位元、差值非線性介於-0.81~0.86LSB之間、積分非線性介於-0.63~1.04LSB之間、功率消耗為7.65mW。

關鍵字

雙斜率式類比數位轉換器；連續逼近式類比數位轉換器；開關電容式積分器

並列摘要

Digital signal processing (DSP) is becoming popular and an analog-to-digital converter (ADC) is an essential component there because every signal in natural world is analog. Among many types of ADC, dual slope ADC and successive approximation register ADC (SAR ADC) are good candidates for low power applications. A dual slope ADC is one of integrating ADCs providing high resolution, high accuracy, and noise rejection. But, its major disadvantage is low conversion rate. On the other hand, the SAR ADC architecture is well suitable for bio-medical applications due to its moderate speed and low-power consumption. In this research, the hybrid architecture combines SAR ADC and dual slope ADC in a two-step conversion. SAR ADC converts 6 bits of MSBs, and then dual slope ADC converts 4 bits of LSBs. SAR ADC consists of dual sampling capacitor, sample-and-hold circuit (S/H), digital-to-analog converter (DAC), comparator, and successive approximation register. The structure of dual slope ADC consists of Miller sample-and-hold circuit, switched-capacitor integrator, comparator, and counter. In this research, 10-bits 5KS/s Hybrid ADC under a single 1.8V power supply has been designed and simulated in TSMC 0.18μm CMOS 1P6M process. Simulation results show that Hybrid ADC can operate at an input frequency of 92.7Hz with SFDR of 51.2dB and SNDR of 50.1dB. The peak DNL is -0.81LSB ~ 0.86 LSB, the peak INL is -0.63LSB ~ 1.04LSB, and the power dissipation is about 7.65mW.

並列關鍵字

Dual Slope ADC ； Successive Approximation ADC ； Switched-Capacitor Integrator

參考文獻

[1]Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design,” Oxford University Press, Inc. 2002.

[2]David A. Johns, K. Martin, “Analog Integrated Circuit Design,” John Wiley and Sons Publishers, 1997.

[6]P.W. Li, M. J. Chin, P.R. Gray, R. Castello, “A ratio-independent algorithmic analog-to-digital conversion technique,” IEEE Journal of Solid-State Circuits, vol. 19, issue 6, Dec. 1984, pp. 828-836.

[7]Behzad Razavi, “Principle of Data Conversion System Design,” John Wiley and Sons Publishers, 1995.

[8]Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500KS/s low power SAR ADC for bio-medical applications,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 228-231.

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1.8伏特十位元混合式類比數位轉換器的設計與製作

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