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  • 學位論文

以電化學原子層沉積Cu(Mn)薄膜的研究

Studies of Cu(Mn) Thin Film by Electrochemical Atomic Layer Deposition (EC-ALD)

指導教授 : 方昭訓
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摘要


近年來超大型積體電路要擴展到更小的尺寸,根據ITRS國際半導體技術藍圖指出在2020年銅製程銅金屬線寬間要低於36 nm,而阻障層厚度必須降至約1.1 nm,必須要讓材料的形成只有幾個奈米厚,使孔洞之深寬比加劇,因此,原子層沉積與電化學的結合發展成電化學原子層沉積(EC-ALD)得以解決新世代半導體製程之挑戰。 本研究分為兩大部分: 第一部分 : 探討在矽基板上以濺鍍方式沉積Ru (10 nm)薄膜作為晶種層,在不同pH值溶液和沉積電位下,以電化學原子層沉積製備銅薄膜。製程利用表面侷限氧化還原反應(SLRR),將鉛以欠電位沉積(UPD)鍍在釕薄膜上作為犧牲層,然後由銅溶液中的Cu2+開路電壓取代鉛形成原子層銅薄膜,經熱處理後探討其熱穩定性。實驗以四點探針(FPP)分析電性、表面輪廓儀(Alpha-Step)測量膜厚、X光繞射儀(XRD)進行結構分析、場發射掃描式電子顯微鏡(FE-SEM)分析表面形貌、化學分析光譜儀(ESCA)進行成份分析。 實驗結果顯示以電化學原子層沉積成功製備出銅薄膜,分析結果顯示,本實驗研究溶液pH值為3太過酸性會將Ru薄膜剝離掉;pH值為4以上容易氧化;pH值高於5之後容易形成氫氧化物薄膜均勻性差;pH值為3.5均勻性佳為最理想薄膜。沉積電位取決於循環伏安圖(CV)的還原峰電位附近,如果選擇還原峰電位為大量沉積,電位取決要經過分析選擇適合原子層沉積的電位,其中Cu UPD (-0.04 V) 和Pb UPD (-0.46 V),pH 3.5,初鍍膜具有最低電阻率26.41 μΩ-cm,約175 nm厚,鍍率3.5 nm/cycle。另外在溶液中添加少量聚乙二醇(抑制劑)與尿素(平整劑)之後,對在Ru薄膜上鍍上銅薄膜緻密性大為提升,可降低薄膜厚度與電阻率。 第二部分 : 探討在矽基板上以濺鍍方式沉積Ru (10 nm)薄膜作為晶種層,在不同pH值溶液和沉積電位下,以電化學原子層沉積製備Cu(Mn)薄膜。製程利用表面侷限氧化還原反應(SLRR),將鉛以欠電位沉積(UPD)鍍在釕薄膜上做為犧牲層,然後由銅溶液中的Cu2+開路電壓取代鉛形成原子層銅薄膜,再以錳(UPD)鍍上疊層,以不同銅(SLRR)與錳(UPD) Cycle數作比較,經熱處理後探討其熱穩定性。 實驗結果顯示以電化學原子層沉積可製備出Cu(Mn)薄膜,錳的摻雜可以有效的提高熱處理溫度,而不使銅擴散與矽基板反應生成銅矽化合物與劇烈的晶粒成長導致銅薄膜破裂現象之發生。

並列摘要


International Technology Roadmap for Semiconductors (ITRS) indicates that metal wiring pitch should be reduced to 36 nm in 2020, and the barrier layer thickness must be reduced to about 1.1 nm. As the aspect ratio increases, the gap filling capability will need to be improved. To resolve the issues, electrochemical atomic layer deposition (EC-ALD) was used to prepare Cu and Cu(Mn) films in the study. The study is divided into two parts: Part one : To investigate different pH values and the deposition potential, the copper thin films prepared by electrochemical atomic layer deposition on Ru (10 nm)/Si substrate were performed. The mechanism of deposition used surface limiting redox reaction (SLRR). Pb (UPD) was used to form a sacrificial layer on the Ru film, and then Pb atoms were replaced by Cu2+ in a copper solution under an open circuit voltage to form a Cu thin film layer. The failure mechanism and the thermal stability of Cu/Ru/Si were discussed thereafter. The resistance of the film was measured by a four-points probe (FPP). The thickness of film was measured by surface profiler (α-Step) and crystal structure was analyzed by x-ray diffraction (XRD). The surface morphology was observed by Field-emission scanning electron microscope (FE-SEM) and the composition of thin film was analyzed by electron spectroscopy for chemical analysis (ESCA). The experimental results indicated that the copper films can be successfully prepared by electrochemical atomic layer deposition. The results also showed that the pH value of 3 induced the Ru film delamination during the deposition; pH value of 4 induced film to oxidize; for pH values above 5, a hydroxide Cu film formed to deteriorate the film; pH value of 3.5 was the optimum condition. Deposition potential strongly depends on the reduction potential in cyclic voltammetry (CV) measurement. The results showed that the lowest resistivity of 26.41 μΩ-cm can be obtained by at a condition of Cu UPD (-0.04 V), Pb UPD (-0.46 V), and pH 3.5. The deposition rate was 3.5 nm/cycle. The thickness and resistivity of the film were improved when adding PEG (suppressor) and Urea (leveler) in the solution. Part two : To investigate Cu(Mn) thin films prepared by electrochemical atomic layer deposition, the process was performed Cu (SLRR) and Mn (UPD). The failure mechanism and the thermal stability were discussed thereafter. Cu(Mn) film can be prepared by ECALD. Mn addition can effectively increase the thermal stability of the film. Therefore, the film can prevent Cu diffusion to the substrate to form Cu-Si compounds. Cu(Mn) film can also prevent the grain growth and improve the adhesion.

參考文獻


[1] 2013, The International Technology Roadmap for Semiconductor, ITRS.
[2] J. L. Freeman, Jr., 1993, in Handbook of Multilevel Metallization for Integrated Circuits, S. R. Wilson, C. J. Tracy, and J. L. Freeman, Editors, Noyes Publications, Park Ridge, NJ.
[3] L. Peter, 1998,“Pursuing the perfect low-.kappa. dielectric”, Semicond. Int., pp. 64, September.
[4] S. P. Jeng, R.H. Havemann, M. C. Chang, 1994,“Process integration and manufacturability issues for high performance multilevel interconnect”, Mater. Res. Soc. Symp. Proc. , 25, pp. 337, April.
[5] L. Peters, 1998 “Advancing aluminum interconnect technology”, Semiconductor International, 83.

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