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  • 學位論文

覆晶黏著封裝技術應用於高功率發光二極體之研究

The flip chip and die-attached technique applied on the package of high power LEDs

指導教授 : 陳文瑞
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摘要


本實驗以覆晶(Flip-chip)方式將高功率LED封裝在矽副載置片(Si Submount),用以解決傳統LED封裝中散熱不佳與無法陣列式封裝以減少封裝時所需面積。使用微機電系統(Micro-electromechanical Systems,MEMS)技術與氫氧化鉀(KOH)溶液在副載置片上蝕刻出想要的圖形與深度,再利用電子槍蒸鍍(E-GUN)與電鍍方式沉積所需之電極層。此實驗技術成熟後預計使用晶圓級技術封裝 (Wafer Level Packaging)可大量模組化製作副載置片並降低製作成本,而電鍍方法增厚電極層也可降低成本並且增加其可靠度。 實驗中我們分別研究電極未電鍍上銅與電鍍銅之差異,未鍍上銅之電極是以Ti/Au 250nm作為電極其電阻值會隨著距離而增加,最短電傳導距離電阻值高達4Ω,當高功率LED操作在350mA下則會有1.4V的壓降產生在電路中,導致LED起始工作電壓由3.8V提高至5.2~6.5V。 這使接面溫度量測中的K值與斜率偏移,導致計算出的接面溫度偏高。因此我們使用電鍍銅的方式將副載置片的電極增厚,不僅有效的降低LED的起始工作電壓並且可以增加熱由電極傳導出去時的截面積。並研究不同銅厚度是否影響其導電率與散熱速度。

關鍵字

覆晶封裝 矽基板 副載置片

並列摘要


In this experiment, the flip-chip technology is used to package the high power LED on the Si submount for solving the poor heat elimination in the traditional method and decreasing the package area by array package. The Micro-electromechanical Systems technology and KOH solution are used to etch the shape and depth on Si Submount, then the electron gun and electroplating are used to deposit the electron conduction layer thick. Once the packaging technology become mature, it expects to use wafer level packaging to mass produce submounts by modulization and reduce the manufacturing cost. Moreover, using electroplating method to increase the electron conduction layer thick could not only reduce the manufacturing cost but also increase the package reliability. In this experiment, we research the difference between the electron conduction layer coated with and without Cu. The layer coated without Cu is made by electron gun with Ti/Au 250nm, and the electric resistance will increases along with the increase of distance. The electric resistance of the shortest electron conduction comes to 4Ω. When the high power LED operates at current 350mA, it generates 1.4V voltage drop in the circuit. And it makes LED operation voltage increase from 3.8V to 5.2~6.5V. The slope shift affects the K value of the junction temperature and leads to the calculated junction temperature value higher. For this reason, in this research the Cu electroplating is applied to increase the thickness of the electrode on Si submount. This can not only decrease the threshold voltage of LED at 3.8V but also increase the cross-sectional area when heat transmitted by electrode. We also research the impact of Cu thickness on electric conductivity and heat dissipation rate.

並列關鍵字

Flip-chip Si-submount

參考文獻


參考文獻
[1] S.C.Bera, R.V.Sindh and V.K.Garg, “Temperature and Compensation of Light-Emitting Diode,” IEEE Photonics Technol.Lett, pp. 2286-2288, (2005)
[2] C. Tsou*, Y.S. Huang and G.W. Lin, “Silicon-based Packaging Platform for Light Emitting Diode”, Electronic Packaging Technology, 2005 6th International Conference, pp. 1-6
[3] W.K. Jeung, S.H. Shin, S.Y. Hong, S.M. Choi, S. Yi, B. Yoon, H.J. Kim, S.J. LEE and K.Y. Park, “Silicon-Based, Multi-Chip LED Package”, Electronic Components and Technology Conference, pp.722-727, (2007)
[4] J.S. Shie and S.H. Yu, “A micromachined silicon-submount package for vertical emission of edge emitting laser diodes”, Sensors and Actuators A: Physical, vol. 82, pp.297-301, (2000)

被引用紀錄


江岳霖(2010)。應用高導熱膜層於高功率發光二極體散熱效果之研究〔碩士論文,國立虎尾科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0028-0308201014224300
顏昊朋(2011)。以化學氣相沉積法成長類鑽碳薄膜之特性研究〔碩士論文,國立虎尾科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0028-1901201118405500

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