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  • 學位論文

採用多相位連鎖數位控制震盪器陣列的可合成注入式鎖相迴路

Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays

指導教授 : 周世傑

摘要


本論文提出一個採用多相位連鎖數位控制震盪器陣列的可合成注入式鎖相迴路。透過一輔助環的協助下將兩個原本相位互相獨立的數位控制震盪器連鎖在一起,產生一多相位數位控制震盪器陣列。除此之外,在注入式鎖相迴路中,也採用頻率追蹤迴路將傳統的鎖相迴路路徑和相位注入的路徑分開,使得傳統的注入式鎖相迴路中的競態條件得以被解決。 晶片設計利用TSMC 40nm GP 1P10M CMOS製程進行電路模擬與實現,除了少數元件是自行建立的元件庫外,皆使用元件廠所給予的標準元件,因此設計可以很容易的轉換到其它製程。整體電路的核心面積為0.01876平方毫米。操作在輸出訊號為5.024億赫茲的情況下,模擬所得到的週期抖動為百分之0.048單位間隔。此電路可有8相位信號且操作的輸出訊號為5.024億赫茲且輸入參考時脈訊號為78.5百萬赫茲時,整體功率消耗為6.2毫瓦特。

並列摘要


A synthesizable injection-locked phase-locked loop with multiphase interlocking digitally controlled oscillator arrays is proposed in this thesis. By using an auxiliary ring, it interlocks two digitally controlled oscillators (DCOs) together to create a multiphase interlocking digitally controlled oscillator arrays. By doing interlocking of two DCOs, the number of phase provided can be double and the oscillation frequency can be as fast as the original two stage differential DCO. Moreover, it also adopts frequency tracking loop to separates the injection path from the traditional PLL path in the ILPLL, so the race condition in the traditional ILPLL can be resolved. The chip has been designed and implemented in TSMC 40nm GP 1P10M CMOS process technology. In the proposed synthesizable ILPLL, all logic cells and circuit components are using standard cell provided by foundry and our group. Therefore, it can be easily migrated from one technology to another. The total area of the synthesizable ILPLL core is only 0.01876mm2 and provide 8 phase output. The simulated RMS jitter from a 5.024GHz output frequency is 0.048% UI. The total power consumption is 6.213mW at 5.024GHz output frequency and 84MHz reference clock.

並列關鍵字

ADPLL ILPLL Multiphase IDCO Synthesizable

參考文獻


[1] V. Kratyuk, P. K. Hanumolu, U. Moon, and K. Mayaram, “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 54, no. 3, pp. 247–251, Mar. 2007.
[2] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, “A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp.42–51, Jan. 2008
[3] W. Deng, et al., "A 0.0066 mm2 780 μW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-Coupled Oscillator Using Edge-Injection Technique," IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2014, pp. 266-267
[4] ANALOG DEVICES, Fundamentals of Phase Locked Loops (PLLs), Tutorial MT-085. Available: http://www.analog.com/media/en/training-seminars/tutorials/MT-086.pdf
[5] A. Aktas and M. Ismail, CMOS PLLs and VCOs for 4G Wireless, Springer, 2004.

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