三維積體電路低溫銅對銅直接接合技術之結構製程開發與其電性量測

Process Development and Electrical Investigation of Pillar-Concave Structure for Low Temperature Cu-Cu Direct Bonding in 3D Heterogeneous Integration

李建辰(Jian-Chen Li)

指導教授 ： 陳冠能

國立交通大學/電機學院/電子工程系所/碩士(2018年)

摘要

隨著尺寸持續的微縮，元件製程已快到達物理極限，傳統的二維積體電路面臨製程瓶頸與高成本問題，而三維積體電路被視為是延續摩爾定律的關鍵技術。其利用垂直堆疊晶片的方式，縮小元件封裝面積，降低訊號傳遞的電阻電容延遲，並達成低功耗、不同基板間的異質整合目標。在三維積體電路的關鍵技術中，晶片接合扮演重要的角色，其中金屬對金屬接合具有良好的導電導熱性質跟穩固的機械強度，更是被廣泛應用在先進半導體封裝技術上。在所有金屬材料中，銅具有傑出的導熱性和低電阻率，因此是現在金屬接合的主流。
傳統的銅對銅接合製程，必須要300oC以上的高溫才能達到良好的接合結果。然而隨著元件持續的微縮跟精細，熱預算問題成為製程的考量。高溫接合條件不僅使元件損壞，不同材料間熱膨脹係數造成的應力跟對準誤差也是重要考量。因此，許多低溫的銅對銅接合技術被提出，但是每種方法都有其困難度跟挑戰性，甚至不符半導體量產的經濟利益。本實驗室先前提出一種嶄新的低溫銅對銅直接接合技術，在一大氣壓、200oC接合溫度、10分鐘接合時間的條件下，利用銅柱跟銅凹洞結構，搭配沉積在矽基板上具有感光性的高分子材料，成功實現低溫銅對銅直接接合製程。由於接合時會產生大應力，使得銅柱變形填滿整個結構，並因為應力釋放的額外熱能，提供接合所需的能量，以實現低溫下銅對銅直接接合的目標。透過先前的模擬結果發現，銅凹洞結構的側壁角度對接合時應力釋放大小有直接影響。因此本實驗搭配重新佈局層及高分子材料的黃光測試，開發出更大應力的側壁角度的銅凹洞結構，並實現在一大氣壓、150oC跟200oC接合溫度、1分鐘接合時間的條件下接合成功。其中，重新佈局層是利用金屬掀離製程搭配雙層光阻結構，解決傳統正光阻在掀離過程中圖案邊緣有多餘金屬殘留的問題。此外，透過剪切測試、表面粗糙度分析、電性和可靠度分析，證實此結構具有高接合強度、溫度跟濕度的高穩定性、還有表面粗糙的高容忍度。本製程開發的低溫銅對銅接合技術，相信未來極具潛力應用在不同基板上，以實現三維異質整合目標。

關鍵字

三維積體電路 ； 設計結構 ； 低溫結合 ； 銅接合

並列摘要

Three-dimensional integrated circuit (3D IC) has been developed to extend Moore’s law with the advantages of small form factor, low power consumption and low RC delay. Among the key technologies of 3D IC, metal-to-metal bonding for vertical stacking is widely used to achieve 3D heterogeneous integration, and Cu is the best option due to its outstanding thermal conductivity and low resistivity. Conventional Cu-Cu bonding requires high bonding temperature more than 300oC to accomplish good bonding quality. However, as the device is scaling down, the requirement of thermal budget is more critical than before. High bonding temperature would give rise to device degradation and misalignment during bonding process. Therefore, several Cu-Cu bonding approaches have been developed under low temperature bonding condition, yet there still exist some drawbacks in the fabrication process, such as high cost and less application in reality.
Based on previous research results, low temperature Cu-Cu direct bonding in pillar-concave structure using polyimide as concave layer was presented. For pillar-concave structure, high stress can cause pillar deformation and produce extra heat energy, which can help achieve well-bonded structure in the low temperature condition. In review of the previous bonding structure, low bonding temperature of 200oC and bonding duration of 10 minutes under atmospheric pressure was fulfilled. Moreover, the result of simulation shows that the sidewall angle of concave structure greatly affects stress during bonding process. In this thesis, different kinds of sidewall angle of polyimide profiles were fabricated by lithography process. With the assistance from previous simulation work, the optimized polyimide profile was obtained for subsequent Cu concave structure. The redistribution layer was fabricated by lift-off process using LOR/SU-8 bilayer, which can solve the metal residue problem encountered when using positive photoresist. With the optimized sidewall angle of polyimide for concave structure, pillar-concave structure was bonded successfully with low bonding temperature of 150 ~ 200oC and bonding duration of 1 minute under atmospheric pressure.
Moreover, after carrying out the shear test and analyzing the surface roughness, electrical characteristics as well as reliability performance, pillar-concave structure indeed shows good mechanical strength, stable resistance and large tolerance of roughness. With many advantages mentioned above, pillar-concave structure presented in this thesis has promising potential to be applied on different substrates, such as glass wafer and printed circuit board for future 3D heterogeneous applications.

並列關鍵字

3D IC ； Pillar-concave structure ； Low temperature bonding ； Cu-Cu bonding

參考文獻

[1] W. F. Brinkman, D. E. Haggan and W. W. Troutman, "A history of the invention of the transistor and where it will lead us," IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 1858-1865, 1997.

[2] J. S. Kilby, "Invention of the integrated circuit," IEEE Transactions on Electron Devices, vol. 23, no. 7, pp. 648-654, 1976.

[3] R. R. Schaller, "Moore's law: past, present and future," IEEE spectrum, vol. 34, no. 6, pp. 52-59, 1997.

[4] Intel Technology and Manufacturing Day, "Moore's law leadership," [Online]. Available: https://newsroom.intel.com/tag/2017-manufacturing-day/

[5] C. h. Yu, "The 3rd dimension-More Life for Moore's Law," in 2006 International Microsystems, Package, Assembly Conference Taiwan, 2006, pp. 1-6.