垂直堆疊全包覆奈米薄片多晶矽無接面互補式金氧半電晶體

Investigation on Vertically Stacked Gate-All-Around Nanosheet Poly-Si Junctionless CMOS Transistors

張智堯(Chih-Yao Chang)

指導教授 ： 趙天生

國立交通大學/理學院/電子物理系所/碩士(2018年)

摘要

與以往使用Si/Ge 多層結構或深反應性離子蝕刻不同，本研究中使用的是簡易的兩步驟乾蝕刻搭配濕蝕刻製程，成功的製作出多晶矽奈米薄片垂直堆疊全包覆式無接面場效電晶體。其中的矽奈米薄片由光罩寬度為40 奈米製作出的實際高度與寬度各別8奈米與30奈米，而有效的寬度是76奈米。在元件製作完成後，從不同的閘極長度與通道寬度切入，我們廣泛的討論了兩種型態的多晶矽奈米薄片垂直堆疊全包覆式無接面場效電晶體的電性。
近一步地，我們以同樣的製程成功的製作出多通道的多晶矽奈米薄片垂直堆疊全包覆式無接面場效電晶體，其靜電控制能力與次臨界特性的表現都非常卓越。兩種型態的導通狀態電流也有顯著的提升。同時，我們也在單通道的元件中觀察到浮動閘極所導致的閘極控制能力下降的情形。另外，經過比較，我們也發現解決的方法是藉由調控離子佈植時的能量來調控摻質的深度。利用這個方法，可以調整兩種型態的導通狀態電流大小。在研究中，我們有效的提升N型雙層多晶矽奈米薄片垂直堆疊全包覆式無接面場效電晶體的導通狀態電流大小，使兩種型態的導通狀態電流在相同的數量級，並應用在補償式金屬氧化物半導體反相器。最後，我們展示了一個經過優化後補償式金屬氧化物半導體反相器完美的電壓傳輸特性。

關鍵字

垂直堆疊 ； 全包覆式閘極 ； 奈米薄片 ； 無接面

並列摘要

The GAA Nanosheet Poly-Si JL FETs have been successfully fabricated by only two simple steps that the dry etching process follows by wet etching. The dimension of gate stack of WM = 40 nm with Hp,1 × Wp,1 of top layer poly-Si is 8 nm × 30 nm, and Weff is 76 nm. Then, we comprehensively discuss the electrical characteristic of the GAA Nanosheet Poly-Si JL FETs with two different type MOS transistors, gate length and channel width.
Furthermore, vertically multiple channel architecture devices are also have been successfully fabricated by the same process and behave superior electrostatic control ability and subthreshold characteristics performance. The on-state-current in two different type have significantly boosted up, respectively. The floating-gate-induced gate control ability degradation resulting is observed from single channel devices. It is attributed to the difference of doping profile. Furthermore, we discover that through the adjustment of energy of ion implantation, the ION of 2 Layer Nanosheet n-type JL FETs has effectively boosted up close the level of 2 Layer Nanosheet p-type JL FETs. Finally, the VTC of CMOS inverter display a most perfect performance of the VTC of CMOS inverter.

並列關鍵字

Vertically Stack ； Gate-All-Around ； Nanosheet ； Junctionless

參考文獻

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