容忍資料讀取失誤延遲技術的能耗效率實測-使用Wattch功耗模型

Energy Efficiency Measurement of Tolerating Load Miss Latency Techniques - Using Wattch Power Model

陳永志(Yung-Chih Chen)

指導教授 ： 鍾崇斌

國立交通大學/資訊學院/資訊學院資訊學程/碩士(2017年)

摘要

現代處理器雖然在架構設計上可能有所差異,但通常是使用許多共通的基本硬體單元建構而成。 可以透過一套共通的功耗模型來進行基本硬體單元能耗的模擬與評估。
透過將Wattch 功耗模型實施到不同容忍資料讀取失誤延遲技術，本研究對這些技術進行效能與能耗效率的實測，用以確認不同計算機架構設計在運算性能以及能耗效率的差異。
透過實測結果我們觀察到容忍資料讀取失誤延遲技術可以在那些會造成較高LLC資料讀取失誤指令比率與延誤執行週期的評估指標上取得很好的能耗效率改進，另一方面在其他評估指標上則可能會依照不同技術而有不同程度的能耗效率減損。
我們也發現採用Preserving Buffer為基礎的設計相比於指令窗硬體擴展的設計，在可承受的能耗效率減損代價上，可以擁有更好的硬體擴展可行性。

關鍵字

能耗效率 ； 功耗模型 ； 資料讀取失誤延遲

並列摘要

Although modern processors differ in architectural design, they are often constructed using a number of common basic hardware units. We can carry out the basic hardware unit energy consumption simulation and evaluation by using a set of common power model.
By applyg the Wattch power model on the different tolerating load miss latency techniques’ performance simulator, this study carries out the energy efficiency measures of these techniques to confirm the differences in computing performance and energy efficiency across different computer architecture designs.
Through the measured results we observed that latency-tolerant techniques can get better energy efficiency improvement at benchmarks which have higher LLC data load miss ratio and blocking cycles, otherwise, these techniques may get energy efficiency degradation at other benchmarks.
We also find PB-based design can have good hardware extension feasibility with affordable energy efficiency degradation compared to EIW-based design.

並列關鍵字

Wattch ； Energy Efficiency ； SimpleScaler ； Preserving Buffer ； Load Miss Latency

參考文獻

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