低功率應用之三五族異質結構奈米線於(111)矽基板的磊晶成長與特性分析

Growth and Characterization of III-V Heterostructure Nanowires on Si (111) Substrate by MOCVD for Low Power Applications

康克拉(Ramesh Kumar Kakkerla)

指導教授 ： 張翼

國立交通大學/工學院/材料科學與工程系所/博士(2018年)

摘要

本論文主要研究以有機化學氣相沉積法於矽基板上成長砷化銦奈米線以及砷化銦/銻化鎵奈米異質結構。在成長三五族砷化銦/銻化鎵奈米結構中，利用場發式掃描電子顯微鏡和高解析度穿透式電子顯微鏡，以及傅里葉轉換和能量色散X-射線光譜分析銻化鎵殼層厚度，探討其晶體和奈米結構的化學成分。
第一部份主要探討成長溫度對於銦化砷奈米線的表面形貌和成長速率之影響。藉由成長溫度控制銦化砷奈米線的直徑和長度。並成功的在矽基板<111>方向成長砷化銦奈米線。除了砷化銦奈米線沿著<111>方向成長之外，其同時擁有閃鋅礦與纖鋅礦混合之結構，可歸因於奈米線堆疊排序時能量差距較小，進而形成多晶型晶體結構。最後，藉由優化氣體流量和成長溫度等條件成長三種不同高品質之砷化銦奈米線 (纖鋅礦結構/閃鋅礦結構/多晶體結構)。
第二部份探討其成長溫度對銻化鎵於砷化鎵奈米線上表面形貌和成長速率之影響。藉由成長溫度控制銻化鎵之殼層厚度。並觀察銻化鎵成長溫度對於烷基分解之影響。隨著銻化鎵成長溫度提高，其吸附原子擴散係數增加，而導致銻化鎵殼層成長速率之影響。並利用場發式掃描電子顯微鏡和高解析度穿透式電子顯微鏡分析成長溫度影響之外。在砷化鎵/銻化鎵奈米異質結構中，藉由不同的五三比的成長條件下，觀察吸附原子對於成長模式之影響。
第三部份探討成長銻化鎵在不同晶體結構之砷化銦奈米結構之影響。利用上述不同的晶體結構之砷化銦奈米結構上，藉由優化成長條件成長具有高品質銻化鎵殼層之研究。接著我們利用TCAD軟體模擬砷化銦/銻化鎵奈米異質結構，探討其核層與殼層厚度對於場效電晶體間隔層之影響，並觀察其元件的導通電流大小為主要關鍵之因素，而我們發現元件的導通電流可藉由在間隔層的長度以提高的極限值。最後，我們成功的將此砷化銦/銻化鎵奈米結構製作出單根奈米元件，並量測此元件之歐姆接觸特性，從反斜率可計算出此奈米元件阻值約為3.4 -cm。由此證明藉由砷化銦/銻化鎵奈米結構未來亦可應用於次世代低功率半導體元件。

關鍵字

機化學氣相沉積系統

並列摘要

In this thesis, the growth and characterization of vertically aligned Au-free InAs and InAs/GaSb heterostructure nanowires (NWs) on Si (111) substrate by Metal Organic Chemical Vapor Deposition (MOCVD) are studied. Field-emission scanning electron microscopy (FEG-SEM), high resolution transmission electron microscopy (HR-TEM), fast fourier transform (FFT) and energy dispersive x-ray spectroscopy (EDX) analysis measuremen¬ts have been used to investigate the morphology, GaSb shell thickness, crystal structures, and chemical compositions of the NWs.
The effect of growth temperature on the morphology and growth rate of the InAs NWs is investigated. Control over diameter and length of the InAs NWs is achieved by varying the growth temperature. All the InAs NWs were grown layer by layer in 〈111〉direction. Due to a very small energy difference between the two Wurtzite (WZ) and Zinc-blende (ZB) phases for InAs along 〈111〉growth direction, a small change in the sequence of the layers in 〈111〉growth direction can easily lead to the change in the WZ and ZB crystal structures, resulting in mixture of WZ and ZB phases i.e, polytype crystal structure. A combination of optimized gas flow rates and growth temperature has given good crystal quality of InAs nanowires. Pure crystalline WZ InAs NWs were grown using the properly controlled growth parameters. Pure ZB InAs NWs are grown by adding antimony (Sb) during the growth.
The effect of growth temperature on the morphology and growth rate of the GaSb on InAs NWs is investigated. Control over the GaSb shell thickness is achieved by using growth temperature. As the GaSb growth temperature increase, GaSb radial growth rate increases due to the increase in alkyl decomposition at the substrate surface. Diffusivity of the adatoms increases as the GaSb growth temperature increase which results in tapered GaSb shell growth. SEM and TEM measuremen¬ts revealed that the morphology and shell thickness can be tuned by the growth temperature. Electron microscopy also shows the formation of GaSb both in radial and axial directions outside the InAs NW core can be controlled by the growth temperature. GaSb shell thickness is also controlled by the growth time. The effect of V/III ratio variation on the morphology and growth rate of the GaSb on InAs NWs is also investigated. GaSb is grown under three different V/III ratios, while keeping the growth temperature and TMSb flux constant. Ga adatoms are observed to have no influence on GaSb shell growth rate. But, Ga droplets form on the nanowire tips and GaSb axial growth is observed when a relatively higher TMGa flow rate is used. Whereas, the droplets are missing and only radial GaSb shell is observed for low TMGa flow rate.
The growth of GaSb on various InAs nanowire crystal structures is investigated. The GaSb is grown radially and axially on WZ, ZB and Polytype (mixture of WZ and ZB) InAs nanowires. The effect of the various InAs crystal structures on GaSb is studied. InAs NWs with Polytype, WZ and ZB crystal structures were grown using the properly controlled growth parameters. The GaSb was grown on polytype InAs core resulted in the same polytype GaSb shell. Whereas, axially grown GaSb possesses ZB structure. In case of InAs NW with WZ structure, a very good crystalline WZ GaSb shell was obtained. Surprisingly, axially grown GaSb also has the InAs core crystal structure (WZ). Axially grown GaSb possessing WZ crystal structure has never been observed before even using the external catalyst. For ZB InAs NW, both axially and radially grown GaSb have the ZB structure.
Simulation of InAs/GaSb heterostructure nanowire based Tunnel Field Effect Transistor (TFET) is performed using Synopsys’s Sentaurus TCAD. The effects of device intrinsic parameters such as shell thickness, spacer length on the performance of the InAs/GaSb nanowire Tunneling FETs are investigated. Device on-current (ION) was chosen as the key figure of merit in this study. ON-current initially increases with radius up to 2 nm shell radius thickness and then starts to decrease. This increase in ON-current for a thin shell around core is attributed to the injection of carriers and the increase in the intrinsic mobility of core than shell. The length of spacer was varied from 1 nm to 5 nm with a step size of 1nm and its effect on Id-Vg was studied. The addition of spacer between source/gate electrodes results in the increase in ON-current and gate capacitance (Cgg) starts to decrease as the length of the spacer increases for core-shell nanowire TFET. It is found that ION can be improves by adding spacer up to a critical limit. To characterize the basic electrical properties of the grown InAs/GaSb heterostructure nanowires, single-nanowire with metal contacts were fabricated. The I – V characteristics show a linear Ohmic behavior so that the device resistivity can be obtained from the inverse slope ( Vsd / Id) of the curve. The calculated resistivity is around 3.4 -cm which is roughly one order of magnitude larger than the previously reported by others for undoped GaSb thin films.

並列關鍵字

MOCVD ； Nanowires ； InAs/GaSb ； TEM ； SEM

參考文獻

References

[1] D. J. Frank, “Power-constrained CMOS scaling limits,” IBM J. Res. Dev., vol. 46, no. 2, pp. 235–244, 2002.

[2] H. Riel, L. E. Wernersson, M. Hong, and J. A. Del Alamo, “III-V compound semiconductor transistors - From planar to nanowire structures,” MRS Bull., vol. 39, no. 8, pp. 668–677, 2014.

[3] E. Pop, “Energy dissipation and transport in nanoscale devices,” Nano Res., vol. 3, no. 3, pp. 147–169, 2010.

[4] W. Y. Choi, B. Park, J. D. Lee, and T. K. Liu, “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV-dec,” vol. 28, no. 8, pp. 743–745, 2007.