擴散電阻的靜電放電特性分析與防護設計上的應用

ESD Characteristics of Diffusion Resistor and its Application in On-chip ESD Protection Design

馮耀武(Yao-Wu Feng)

指導教授 ： 柯明道

國立交通大學/電機學院/電機學院碩士在職專班電子與光電組/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00025

摘要

本論文是針對silicided N+ 擴散電阻和non-silicided N+ 擴散電阻在100奈秒脈衝高電流加壓的條件下作出它的特性化和模型。經由實際量測，這兩種電阻的阻值會隨著脈衝時間的方均根變化。在電阻上的電流會隨加壓時間增加而減少、電阻上的電壓會隨加壓時間增加而增加。電阻在高電流下，造成非線性的電壓－電流特性的原因可以用焦耳熱〈Joule-heating〉引起的電阻阻值改變來說明。另外，本實驗所調查的這兩種電阻在高電流的條件下有不同的特性。因為這種不同的特性，當這兩種電阻被應用在積體電路的靜電放電〈ESD〉防護上時，其所實現的佈局設計要有所不同。

關鍵字

靜電放電

並列摘要

The high current conduction in silicided N+ diffusion resistor and non-silicided N+ diffusion resistor under the 100nsec pulse condition had been characterized and modeled carefully in this work. We find the resistances of both types resistors change with the square root of the stress time. It induces the current decreasing and voltage increasing with the stress time. The root cause of the non-linear IV characteristics of the diffusion resistor under high current stress can be well explained by the Joule-heating induced the resistance change. In additional, we also find that these two diffusion resistors during high current stress will appear some different characteristics. Due to these different characteristics, the silicided device cannot use the same layout as the silicided blocking device on ESD protection design.

並列關鍵字

ESD ； Silicided ； diffusion resistor

參考文獻

[1] G. Krieger and P. Niles, “Diffused resistors characteristics at high current density levels-analysis and application,” IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 416-423, 1989.

[2] K. Banerjee and C. Hu, “High current effects in silicide films for sub-0.25um VLSI technologies,” in Proc. International Reliability Physics Symposium, 1998, pp. 284-292.

[3] D. C. Wunsch and R. R. Bell, “Determination of threshold failure levels of semiconductor diode and transistors due to pulse voltage,” IEEE Trans. Nuc. Sci., vol. 15, no. 6, pp. 244-259, 1970.

[5] P. A. Juliano and E. Rosenbaum, “Accurate wafer-level measurement of ESD protection device turn-on using a modified very fast transmission-line pulse system,” IEEE Trans. Device Mater. Reliab., vol. 1, no. 2, pp. 95-103, 2001.

[6] D. Krakauer and K. Mistry, “ESD protection in 3.3V sub-micron silcided CMOS technology,” in Proc. EOS/ESD Symp., 1992, pp. 250-257.