高壓製程之靜電放電防護設計與閂鎖效應防制研究

ESD Protection Design and Latchup Prevention in High-Voltage BCD Technology

戴嘉岑(Chia-Tsen Dai)

指導教授 ： 柯明道

國立交通大學/電機學院/電子工程系所/博士(2017年)

摘要

隨著高壓製程積體電路於車用電子、面版驅動電路、電源供應器及電源管理等應用的普及化，靜電放電防護能力已成為影響電子產品可靠度的主要因素之一。對於使用在這些應用的輸出輸入介面和作為靜電放電保護元件的高壓擴散式金氧半電晶體 (laterally diffused MOS, LDMOS)而言，除了電晶體本身複雜的元件結構外，其高觸發電壓(trigger voltage)及低持有電壓(holding voltage)的特性，往往使得高壓積體電路的靜電放電防護能力不足，並有可能產生閂鎖效應(latchup)或類似閂鎖效應(latchup-like)的危險。因此如何開發有效的靜電放電防護設計，是目前這些高壓積體電路設計上的重要課題之一。
傳統上，矽控整流器(Silicon-Controlled Rectifier, SCR)因其良好的靜電放電耐受能力而被廣泛作為靜電放電防護元件使用，但由於雙載子注入效應(double carrier injection) 和正回授機制導致的低持有電壓特性，使其困擾於閂鎖效應的風險而難以廣泛應用於高壓積體電路。因此，第二章中提出了一個具有高持有電壓的新型矽控整流器，藉由在其佈局中加入寄生雙載子電晶體(Bipolar Junction Transistor, BJT)結構，可以有效破壞矽控整流器中固有之正迴授路徑，進而提高其持有電壓。另外，有鑑於閂鎖效應為毫秒等級的可靠度測試，針對高壓元件使用傳輸線脈衝系統(Transmission-Line-Pulsing system)量測得到的持有電壓已不具備說服力，因此直流曲線分析儀(DC curve tracer)和暫態觸發閂鎖效應測試(transient-induced latchup test)也被使用來驗證新型矽控整流器的閂鎖效應免疫能力，此新型矽控整流器已於一個0.25微米高壓BCD (Bipolar CMOS DMOS)製程中獲得實驗驗證。
在高壓積體電路製程技術中，為了使高壓電晶體能承受高操作電壓，製程上的複雜度與確保高壓元件可靠度的困難度也隨之增加，如何提高靜電放電防護元件的耐受能力並同時避免閂鎖效應的發生，往往具有相當的困難度與挑戰。因此，第三章提出使用堆疊架構的低壓電晶體作為高壓積體電路的靜電放電防護元件，不僅能避開高壓製程複雜度所導致的可靠度問題，也能籍由堆疊架構針對不同操作電壓調整堆疊個數以符合應用所需之靜電放電防護設計窗口，其靜電放電防護能力已於一個0.25微米高壓BCD製程中獲得實驗驗證，能防護一個監測車用電池模組積體電路之高壓輸入端抵抗高達八千伏特的人體靜電放電模式(Human Body Model, HBM)靜電轟擊。另外，傳統不同操作電壓之電路區塊一般由各自相對應的高壓元件提供靜電放電防護，因此本章節也提出了共享路徑(sharing path)的概念，單一串堆疊之低壓電晶體能夠提供數個不同操作電壓區塊的靜電放電防護，不需額外設計相應之高壓元件，如此不僅能大幅減少佈局面積，降低晶片製造成本，也能提供有效率的靜電流泄放路徑，進一步增加全晶片的靜電放電防護能力。
本論文第四章開始為高壓製程佈局結構之閂鎖效應防制研究。閂鎖效應是CMOS 積體電路產品設計上一項常見的問題，嚴重時可導致晶片損毀無法正常工作，由於高壓積體電路製程的額定電源、供應電壓一般皆高於數十伏特，在高壓積體電路中寄生的矽控整流器，其持有電壓一般皆遠低於其額定電源供應電壓，這意味著閂鎖效應在高壓積體電路中往往是難以避免的，導致閂鎖效應在高壓積體電路中扮演著一個極關鍵的角色。本章節即針對各種不同的元件結構及佈局參數對於閂鎖效應敏感度的相互關係進行研究，藉由不同佈局測試結構與實驗結果驗證，可進一步評估萃取出能通用在高壓積體電路中的閂鎖效應防制之佈局準則。
目前發展的系統單晶片積體電路為了符合產品需求，其系統具有多種電壓準位和不同功能之積體電路，而為了防止不同電路區塊間發生閂鎖效應導致電路功能損毀，不同電壓區塊間需要制訂相關之佈局準則。第五章即針對可能潛在於高壓BCD製程中高壓和低壓電晶體間的寄生閂鎖效應路徑進行研究。在實驗結果中發現了具有低持有電壓的寄生矽控整流器(SCR)路徑，它可能會影響CMOS積體電路產品的靜電放電耐受度，因此，高壓和低壓元件間的佈局準則應嚴謹定義，以避免寄生路徑的發生。
最後，第六章總結了本篇論文的主要結果，並且提出一些關於未來可以持續進行研究的討論。本論文所提出的新型元件設計與測試結構皆搭配實體晶片進行驗證，所有研究成果皆已發表於國際期刊或國際知名學術會議。

關鍵字

高壓製程 ； 靜電放電 ； 閂鎖效應 ； 矽控整流器

並列摘要

Nowadays, the smart power technology has been developed and used to fabricate the display driver circuits, power switch, motor control systems, and so on. However, the process complexity and the reliability of high-voltage (HV) devices have become more challenging compared with the low-voltage (LV) devices. Among the various reliability specifications, on-chip electrostatic discharge (ESD) protection has been known as one of the important issues in HV integrated circuits (ICs). ESD is an inevitable event during fabrication, packaging and testing processes of integrated circuits. ESD protection design is therefore necessary to protect ICs from being damaged by ESD stress energies.
In Chapter 2, the modified silicon-controlled rectifier (SCR) fabricated in a 0.25-μm HV Bipolar-CMOS-DMOS (BCD) technology has been proposed to seek for both effective ESD protection and latchup immunity. Experimental results show that one of the proposed SCRs has a high holding voltage of up to ~30 V in the 100-ns Transmission- line-pulsing (TLP) measurement results. However, through the experimental verification by using transient-induced latchup (TLU) test, the holding voltage of such proposed device decreases to ~20V. It is due to the increased bipolar junction transistor (BJT) current gains of the SCR path induced by the Joule heating effect in the long-term measurement. Such phenomenon is an unavoidable issue that should be carefully taken into consideration when applying SCR device for ESD protection in the HV applications.
In Chapter 3, an on-chip ESD protection solution has been proposed in a 0.25-μm HV BCD process by using LV devices with stacked configuration For HV applications. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-model (HBM) ESD stress. Moreover, stacked LV devices with sharing path technique can be more area-efficient to implement the whole-chip ESD protection in the HV CMOS ICs.
In Chapter 4, the optimization of guard ring structures to improve latchup immunity in an HV double-diffused drain MOS (DDDMOS) process with the DDDMOS transistors has been investigated in a silicon test chip. The measurement results demonstrated that the test devices isolated with the specific guard ring structure of n-buried layer can highly improve the latchup immunity.
In Chapter 5, the latchup path which may potentially exist at the interface between HV and LV circuits in a HV BCD technology has been investigated. Owing to the multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic SCR path featuring a very low holding voltage is found in the experiment silicon chip. It may influence the ESD robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at HV and LV interface should be carefully defined to avoid the occurrence of unexpected parasitic path.
Chapter 6 summarizes the main results of this dissertation, where the future works based on the new proposed designs and test structures are discussed as well. The related works in this dissertation have been published in several international journals or conferences.

並列關鍵字

HV BCD Process ； Electrostatic Discharge (ESD) ； Latch-up ； Silicon Controlled Rectifier (SCR)

參考文獻

[1] B. Baliga, Advanced Power MOSFET Concepts. Springer, 2010.

[2] V. A. Vashchenko and A. Shibkov, ESD Design for Analog Circuits. Springer, 2010.

[3] Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing: Human Body Model (HBM)—Component Level, Standard ANSI/ESDA/JEDEC JS-001-2017, 2017.

[4] Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing―Machine Model (MM)—Component Level, ANSI/ESDA Standard Test Method 5.2, 1999.

[5] Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing―Charged Device Model (CDM)—Component Level, Standard ANSI/ESDA/JEDEC JS-002-2014, 2014.