超薄錫化鍺/鍺結構之N+-P接面及自動對準接觸阻抗測試結構之研究

Studies of N+-P Junctions on Ultrathin GeSn/Ge Structure and Self-Aligned Contact Resistance Test Structure

廖修賢(Hsiu-Hsien Liao)

指導教授 ： 崔秉鉞

國立交通大學/電機學院/電子工程系所/碩士(2018年)

摘要

在本篇論文中，為了優化先進場效電晶體的源/汲極區域，我們針對位於超薄錫化鍺/鍺結構上的N+-P接面進行深入的研究，為了準確擷取低接觸阻抗，我們提出自動對準傳輸線接觸阻抗測試結構，並在高濃度磷摻雜的矽晶片上實現，惜未及在錫化鍺/鍺結構之驗證。
首先，利用磷離子植入及低溫退火，我們實現了具有良好性能的N+-P接面，其中接面之順偏電流密度在順偏電壓為1V的時候高達250 A/cm2；電流開關比則全數大於3×104。除此之外，我們亦利用許多電性測量去分析其漏電流特性及來源。
為了能深入了解載子活化溫度對接面漏電流的影響，我們利用不同的退火溫度來進行N+-P接面的載子活化。我們發現，攝氏350度退火不能消除離子植入造成的缺陷；當退火溫度超過攝氏550度時，接面漏電流會有顯著的上升。根據一系列的電性測量及材料分析，我們提出了一個模型來解釋漏電流的劣化現象，主要機制是離子植入造成錫化鍺以及鍺非晶化，缺陷中的空穴與錫交互作用，加速錫擴散到接近接面處，成為電子-電洞對的激發/複合中心。另外，我們也初步地探討了不同接觸介面與不同載子活化溫度對鎳/錫化鍺接觸阻抗及片電阻的影響，在實驗範圍內並無明顯差異。
另一方面，我們成功地開發了一個新穎的自動對準傳輸線結構(Self-aligned TLM)。藉由自動對準技術來定義接觸窗，可以大大改善傳統傳輸線結構對於側向電流散佈與奈米級微影過程中產生的不理想因素的抵抗能力。我們將此測試結構實現在高濃度磷摻雜的矽磊晶層上，並在這個測量架構下得到一個低達4.7×10−8 Ω-cm2的特徵接觸阻抗值。與此同時，金屬沉積後退火溫度和此結構之接觸窗寬度對於接觸阻抗測量結果的影響亦被討論。最後，我們也在相同的基板上製作了橋式凱爾文電阻(Cross-bridge Kelvin resistor)結構，並用其測量結果來驗證及比對自動對準TLM結構的測量結果，證實自動對準傳輸線結果可以有效避免寄生阻抗的影響，得到較準確的結果。

關鍵字

錫化鍺 ； PN接面 ； 接觸阻抗 ； 測試結構

並列摘要

In this thesis, we thoroughly studied N+-P junctions on ultrathin GeSn/Ge structure and successfully developed a novel contact resistance test structure, aimed for source/drain application in modern Si/Ge-based FETs.
First, well-behaved N+-P junctions possessing high forward bias current density of 250 A/cm2 at −1 V and high On/Off ratio over 3×104 were realized on ultrathin GeSn/Ge Structure using P ion implantation and low-temperature thermal annealing. Also, various electrical characteristic analyses were carried out to investigate the leakage characteristic of these junctions.
Moreover, by performing thermal annealing at different temperatures, we gain an overall insight into the effect of activation temperatures on junction leakage. It is found that the leakage current remains low when samples were annealed at a temperature range of 400oC to 500oC. But, the leakage current of junctions increases drastically when annealing temperatures exceed 550oC. A model is then proposed on the basis of the results of advanced electrical and material characterization to explain ascending junction leakage: A large numbers of defects induced by high-dose ion implantation intermix with Sn atoms escaping from original lattice site. As a result of enhanced Sn diffusion via vacancy-mediated mechanism, Sn atoms come closer to the metallurgical junction of N+-P diode after a high-temperature annealing. These Sn atoms then serve as effective generation-recombination centers in the space-charge region of junction devices. Besides, the effects of activation temperatures and contact interfaces on contact resistance and sheet resistance of Ni/GeSn is preliminarily explored. We observed that all the samples exhibit similar contact characteristics.
On the other hand, a novel test structure called self-aligned TLM (SATLM) was designed and fabricated. By realizing self-aligned contact window definition, the robustness of TLM structure towards lateral current spreading effect and nanoscale contact patterning issues can be greatly improved. Using proposed test structure, we demonstrate significant ρ_c extraction of 4.7×10−8 Ω-cm2 for Ti/Si:P contact. In addition, the influence of post-metal annealing temperatures and contact width on extraction results was discussed. Finally, the extraction results of SATLM were verified and compared with that of CBKR structure fabricated under the identical fabrication processes. The proposed structure is thus confirmed to be less vulnerable to the parasitic elements which limit the measurement accuracy.

並列關鍵字

GeSn ； N+-P Junction ； Contact Resistance ； Test Structure

參考文獻

[1] Y. Kamata, “High-k/Ge MOSFETs for future nanoelectronics,” Materials Today, vol. 11, no. 1-2, pp. 30–38, 2008.

[2] S. Gupta, B. Vincent, D. H. C. Lin, M. Gunji, A. Firrincieli, F. Gencarelli, B. Magyari-Kope, B. Yang, B. Douhard, J. Delmotte, A. Franquet, M. Caymax, J. Dekoster, Y. Nishi, and K. C. Saraswat, “GeSn channel nMOSFETs: Material potential and technological outlook,” in Proc. Symp. VLSI Technol., Jun. 2012, pp. 95–96.

[3] S. Gupta, R. Chen, B. Magyari-Kope, H. Lin, B. Yang, A. Nainani, Y. Nishi, J. S. Harris, and K. C. Saraswat, “GeSn technology: Extending the Ge electronics roadmap,” in Proc. IEDM, Dec. 2011, pp. 398–401.

[4] S. Gupta, Y.-C. Huang, Y. Kim, E. Sanchez, and K. C. Saraswat, “Hole mobility enhancement in compressively strained Ge0.93Sn0.07 pMOSFETs,” IEEE Electron Device Lett., vol. 34, no. 7, pp. 831–833, Jul. 2013.

[5] G. Han, S. Su, C. Zhan, Q. Zhou, Y. Yang, L. Wang, P. Guo, W. Wang, C. P. Wong, Z. X. Shen, B. Cheng, and Y.-C. Yeo, “High-mobility germanium–tin (GeSn) p-channel MOSFETs featuring metallic source/drain and sub-370oC process modules,” in Proc. IEDM, 2011, pp. 402–406.