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  • 學位論文

探索二硫化鉬場效電晶體之介面效應與接觸電阻

Exploring interface and contact effects on MoS2 field-effect transistors

指導教授 : 簡紋濱

摘要


二維層狀材料表現出低維度物理系統特性,為近年來熱門的研究主題。然而,目前的文獻報導,二硫化鉬元件之載子遷移率尚未達到理論預測值,部分學者推估原因為基板中的雜質及接觸電阻,降低元件效能,為此我們探討基板效應與接觸電極特性對二硫化鉬之二維材料元件的影響。 藉由改變不同基板的接觸,譬如將以氮化硼或懸空方式來取代二氧化矽基板接觸,來觀察基板對元件電性影響。以氮化硼作為介電層之二硫化鉬異質結構元件及懸浮二硫化鉬元件,由於氮化硼和懸浮結構設計降低二氧化矽造成之基板介面缺陷,降低介面捕獲電荷密度並提高元件開關效能(subthreshold swing, SS)。此外,相較於二硫化鉬在二氧化矽基板之元件,二硫化鉬在氮化硼基板之異質元件,其蕭特基位障較低且載子遷移率較高。懸浮二硫化鉬元件,卻因懸浮結構之真空電容儲放電荷能力不佳,減低閘極電壓之電場控制載子之能力,減低元件開啟時之電流,且降低了載子遷移率。 在接觸電阻探索方面,我們利用約30奈米以下厚度的石墨烯取代傳統金屬電極,並用撕貼對準機製作場效電晶體元件,由於石墨烯功函數較金電極小且具高導電率,此元件表現出更低的蕭特基位障,且載子遷移率及其他元件性能也都顯著提升。

並列摘要


Two-dimensional (2D) layered materials like MoS2 have become a hot research topic in recent years due to their unique physical properties and transport behaviors. There are some experimental reports showing that MoS2 field-effect transistors (FETs) cannot achieve the ideal performance predicted by theoretical calculations. It is argued that the problems come from either interface trapped charge in the oxide layer or the metal contact resistance. Therefore, we investigate the substrate and the contact effects on the electrical performance of the MoS2 FET devices. To explore the substrate effects, we prepared the MoS2 on hexagonal boron nitride (h-BN) and the suspended MoS2 FETs. Both of the two kinds of the FET devices show a reduction of the interface trapped charge effects from the SiO2 substrate. The interface trap charge densities (D_it) are much lower and the subthreshold swings are lower, indicating a better on-off electric control. In addition, for the FETs of MoS2 on h-BN, the effective Schottky barrier height (∅_B) is lower and the mobility is much higher in comparison with devices of MoS2 on SiO2. On the other hand, for the suspended MoS2 FET devices, the on-state current and the mobility do not show better results because the vacuum between the suspended MoS2 and the substrate decreases the electric gating efficiency. To explore the contact effect, we fabricated MoS2 FET devices with the source-drain metal electrodes replaced by using graphene with thickness less than 30 nm. Because of smaller work function in graphene in comparison with Au, the FET devices show high conductance and much better device performance. The devices also reveal a much lower Schottky barrier and much higher mobility as compared with devices made with Au metal contacts.

參考文獻


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