積層型三維靜態隨機存取記憶體之變異分析及三維讀寫輔助電路設計

SRAM Variation Analysis and Peripheral R/W-Assist Circuits using Monolithic 3D BEOL FinFET Circuits

吳婉琪(Wan-Chi Wu)

指導教授 ： 黃柏蒼

國立交通大學/國際半導體產業學院/國際半導體產業學院/碩士(2019年)

摘要

奈米微縮製程導致導線的電阻及電容的影響變嚴重，三維積體電路設計被應用於解決此相關問題，其中又以積層型三維積體電路的表現效果尤佳。為了避免影響底層的電路特性，上層用低溫結晶法產生多晶矽半導體層；由於多晶矽的結晶的大小與邊界無法預測，使電晶體有不可預測的影響進而影響到電路的功能完整性。在此論文中，利用晶粒邊界控制技術可以限制晶格邊界生成位置，藉由預知晶格邊界，可將靜態隨機存取記憶體的敏感電路放置於晶格內，進而離晶格邊界造成的影響，降低讀寫錯誤率，進而提高積層型三維靜態隨機存取記憶體實現的可能性。
由於積層型三維積體電路技術目前正在發展中，三維靜態隨機存取記憶體的
成本與良率問題皆還需再做更進一步的改善，所以此論文中，亦提出了將讀寫輔助電路及讀寫驅動電路設計於多晶矽層，由於驅動電路對於電流變異性的敏感性較低，所以可以放置上層來降低導線的電阻及電容的影響解降低了晶片面積以降低成本。整體而言，可降低24.8%延遲及19.6%的面積。

關鍵字

積層型三維積體電路 ； 靜態隨機存取記憶體 ； 讀寫輔助電路

並列摘要

Monolithic 3D-IC is an enabling technology for reducing chip size and power consumption and enhancing the overall system performance and using BEOL circuits. To avoid damaging transistors on the bottom silicon layer, low thermal budget is required for while fabricating polycrystalline BEOL circuits on top layers. However, if polycrystalline semiconductor is used, the yield of Monolithic 3D technology is decreased by the random grain boundaries of Si grains. In this thesis, SRAM design using the Location-Controlled-Grain (LCG) technique is presented to reduce the overall bit error rate (BER). Moreover, a graph-based statistical BER analysis is adopted using both transistor-level and cell-level boundary assignments for random grains. The BER of LCG SRAM can be significantly reduced.
The defects of monolithic 3D BEOL circuits is still one of design challenges in monolithic 3D SRAM. Instead of placing SRAM cells on BEOL layers, WL-boosted repeaters and ripple-BL buffers are proposed using monolithic 3D BEOL FinFETs to decrease the catastrophic RC effect of SRAM in sub-10nm technologies. The WL-boosted repeaters and ripple-BL buffers can achieve 24.8% delay reduction and 19.6% area reduction, respectively.

並列關鍵字

Monolithic 3D-IC ； SRAM ； read/write-assist circuit

參考文獻

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