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  • 學位論文

應用於快閃記憶體之2KB EG-LDPC解碼器設計與實作

Design and implementation of a 2KB EG-LDPC decoder for NAND Flash Memory

指導教授 : 張錫嘉

摘要


近年來,快閃記憶體已成為電腦、⼿機、平板以及固態硬碟等裝置的主要儲存 元件,尤其固態硬碟因為價格降低,所以近年來需求⼤幅提升。為了擴⼤儲存容量, 採⽤先進製程或多層儲存單元等技術。但這些技術卻也造成快閃記憶體的資料可靠 度急遽下降。錯誤更正碼是可以有效解決這個問題的⽅法之⼀,以往我們較常使⽤ BCH碼或是RS碼來做為快閃記憶體應⽤上的錯誤更正碼,由於所需更正能⼒與碼 ⻑越來越⼤,BCH與RS碼在硬體上複雜度在這樣的情況下是⾮常⾼的,因此低密 度機偶校對(LDPC)碼逐漸取代這些傳統的錯誤更正碼。⽽快閃記憶體傳輸速度的 提升使得我們需要⾼吞吐量的低密度奇偶校驗解碼器。  在本論⽂中,我們建構出⼀個規格為(18396,16416)的尤拉幾何低密度奇偶 校驗碼。所建構的解碼器具有相當⾼的吞吐量與吞吐量∕⾯積⽐例。且具有良 好的錯誤更正能⼒,碼率為0.892。我們也提出規律的結構與有效率的解碼演算 法,使硬體的複雜度可以降低。以90奈⽶製程實作硬體實現這個解碼器。我們 提出的解碼器吞吐量可以達到16.35Gbps,⽽⾯積為5.97mm2。最後我們也使⽤ Xilinx UltraScale+VCU1525 FPGA來完成繞線的模擬,其時脈為33MHz,吞吐量 為3.37Gbps。

並列摘要


Nowadays, NAND Flash memory has became the main storage component in mobile phones, tablets, Solid-State Disk(SSD), etc. Especially for SSD, due to the lower price, the demand raise rapidly in recent years. With the technology scaling and multi-bit-per-cell technique are adopted to enlarge the storage capacity. Owing to these aggressive technique, the reliability of NAND Flash memory decreases. One of the solutions to reliability issue is soft decision error correction code (ECC) such as Low density parity-check(LDPC) codes. Due to the demand of fast transmission speed of NAND Flash memory, a high-throughput LDPC decoder for NAND Flash applications is desired. In this thesis, we proposed a (18396,16416)Euclidean Geometry(EG) LDPC code for Flash memory application with high data throughput and high throughput to area ratio(TAR). This code have good correcting capability with code rate 0.892. Regular code structure and efficient decoding algorithm are also proposed to lower the hardware complexity. After implemented in 90nm CMOS process, our proposed decoder occupying 5.97 mm2 area can achieve a very high throughput of 16.35Gbps. We also use Xilinx UltraScale+ VCU1525 FPGA to complete the place and rout step, with clock rate 33Mhz and throughput 3.37Gbps.

並列關鍵字

LDPC Finite Geometry Euclidean Geometry NAND Flash ECC

參考文獻


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