內建功率電晶體導通電阻感測電路之直流降壓轉換器設計

A DC-DC Buck Converter Design with Power MOSFETs Turn-on Resistance Variation Detection Mechanism

王威棟(Wei-Dong Wang)

指導教授 ： 蘇朝琴

國立交通大學/電機學院/電機工程系所/碩士(2019年)

摘要

有鑑於電動車產品大量電子化的趨勢，其使用的電源管理系統穩定度及安全性在未來的發展顯得相當重要。在電源管理晶片裡，功率電晶體的損耗程度是其中最具老化意義的代表，其閾值電壓和導通阻抗的量測，往往必須中斷穩壓器的使用，如此繁雜的檢測方式，激發出此論文的構思。
本論文提出了一個線上量測功率電晶體導通電阻之應用，並實現於電壓模式直流同步降壓轉換器。採用隨機取樣方法的責任週期量測電路計算不同數目功率電晶體導通時的責任週期，且再利用電流感測電路以及循序漸近式類比數位轉換器得到負載電阻之大小，最後則是將上述量測電路求得之參數值代入直流同步降壓轉換器之公式求得功率電晶體的導通電阻。
本晶片使用 TSMC 0.25 1P5M HV CMOS 製程，系統操作頻率為1MHz，轉換器最大效能為90.3%，ADC DNL約為 0.5LSB，INL為0.95 ~－0.74LSB。根據理論，藉由20Bit取樣次數計算，導通電阻一個標準差可降低至10% 以內，晶片佈局面積為1662×1540 。

關鍵字

電壓模式同步直流降壓轉換器 ； 電流感測電路 ； 循序漸進式類比數位轉換器 ； 責任週期偵測

並列摘要

As electric vehicles use more and more power electronic devices, the reliability and the safety of power electronic systems become more and more important. In power management IC, Power MOSFETs are the most representative devices affected by aging effects. Traditionally, it is determined by measuring of the threshold voltage and turn-on resistance. However, it has to interrupt the function of power electronic systems and be done off-line. Due to the inconvenient and complicated off-line maintenance, this thesis focuses on-chip and on-line measurement methodology.
This thesis presents an on-line application to measure Power MOSFETs’ turn-on resistance in voltage-mode synchronous DC-DC buck converter. It applies a random sampling technique to measure the duties while different numbers of MOS transistor banks are turned on. A current sense circuit and a successive approximation analog to digital converter are used to obtain the load resistance value. Finally, these values are taken into the formula of synchronous DC-DC buck converter to obtain the turn-on resistance.
The chip is designed in TSMC 0.25 1P5M HV CMOS process. The frequency of the system clock is 1MHz. The maximum efficiency of the converter is 90.3%. The DNL of the SAR ADC is within 0.5LSB and INL is 0.95 ~－0.74LSB. According to the theory, the turn-on resistance error can be reduced to less than 12.5% per standard deviation by 20Bits sampling times. The chip area is 。

並列關鍵字

Voltage-mode Synchronous DC-DC Buck Converter ； Current Sense Circuit ； Successive Approximation Analog to Digital Converter ； Duty Cycle Measurement

參考文獻

[1] The Military Handbook for Reliability Prediction of Electronic Equipment. (MIL-HDBK-217).

[2] S. Dusmez, M. Heydarzadeh, M. Nourani, and B. Akin, "Remaining Useful Lifetime Estimation for Power MOSFETs Under Thermal Stress With RANSAC Outlier Removal, " IEEE Trans. Ind. Informatics, vol. 13, no. 3, pp. 1–1, Jun. 2017.

[3] H. H. Yang, "A Buck Converter Design with Embedded Temperature Sensor and Thermal Balancing Mechanism, " MS thesis, Department of Electrical Engineering and Computer Science, National Chiao Tung University, 2015.

[4] G. F. Zeng "A DC-DC Buck Converter with Built-in Hall Effect Current Sensing Device and Dead Time Control Mechanism," MS thesis, Department of Electrical Engineering and Computer Science, National Chiao Tung University, 2017.

[5] E. Rogers, Understanding buck power stages in switch mode power supplies. Texas Instruments, Mar. 1999.