使用二維低功耗移位控制解決方案在多個 掃描鏈設計的繞線實現

隨著超大型積體電路進入到次微米製程，當積體電路在製造過程中是否有損壞的測試上將面臨許多的挑戰。然而，在多條掃描線的測試方式下可以解決許多測試問題，例如解決測試資料體積大小，測試時間和測試時的功率消耗等問題。再者，利用二維掃描移位控制概念[21]，我們可以容易實現在測試時的低功率消耗、測試時間和測試資料大小以及讓這些方法在成電路時不佔用太多的晶片面積。在此藍圖下，我們將可以忽略大量不需要測試的測試資料且不輸入至電路中做測試，如此可以減少測試資料大小和測試時間。基於這個技術下，此篇論文所做的研究將利用兩種群集方法[17]、[18]下去發展一個有效率的掃描順序，並且能實現在實際的設計流程中。和比較傳統單一一條掃描線方式，在這裡所使用的兩種群集方法，只要適度的調整繞線資源的使用率，此時並不會增大積體電路面積，因此不會增加成本，當然還是會有代價的，就是-繞線會較為擁擠。因此，使用者可以基於編碼效率或是在繞線擁擠度等客觀條件下，在這兩種群集方法下做最佳的選擇並應用。

關鍵字

多條掃描鏈

並列摘要

The migration of VLSI design in submicron technologies has presented several challenges in manufacturing tests. Multiple scan chain schemes solve many testing issues, such as test data volume, test time and test power consumption. Based on a new two-dimensional scan shift control concept [21], we can achieve low test power with simpler implementation and smaller hardware overhead. This scheme skips many unnecessary don’t care patterns to reduce test time and test data volume. Based on this technique, this study applies two clustering approaches in [17] and [18] to develop an efficient scan ordering to achieve modern testing design flow. Compared with the traditional single scan chain, the two clustering approaches have little routing resource overhead. By adjusting the appropriate placement utilization rate within the routable region, the chip area is not increased, but with the price of routing congestion. Users may find a better tradeoff between the encoding efficiency, and routing congestion in both clustering approaches.

並列關鍵字

multiple scan chain

參考文獻

[2] A. Crouch. “Design-for-Test for Digital IC’s and Embedded Core Systems” Prentice Hall, 1999.

[6] Il-soo Lee, Yong Min Hur, T. Ambler, “The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time,” in Proc. of Asian Test Symposium, pp. 94-97, 2004.

[8] M. Nourani, M. Tehranipour and K. Chakrabarty, “Nine-coded Compression Technique with Application to Reduced Pin-count Testing and Flexible On-chip Decompression,” in Proc. of Design, Automation, and Test in Europe, Vol.2, pp. 1284-1289, Feb. 2004.

[9] H. Tang, S. M. Reddy and I. Pomeranz, “On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs,” in Proc. of IEEE International Test Conference, Vol. 1, pp. 1079-1088, 2003.

[10] C.-Y. Lin and H.-M. Chen, “A Selective Pattern-Compression Scheme for Power and Test-Data Reduction,” in Proc. of International Conference on Computer-Aided Design, pp. 520-525, 2007.

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使用二維低功耗移位控制解決方案在多個掃描鏈設計的繞線實現

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