電荷比例式數位類比轉換器之二進位電容陣列的同步電容大小與寄生效應調整之共同質心繞線最佳化

Simultaneous Capacitor Sizing and Parasitic-aware Common-centroid Routing Optimization for Binary-weighted Capacitors in Charge-scaling DACs

蕭偉豪(Wei-Hao Hsiao)

指導教授 ： 林柏宏

國立中正大學/工學院/電機工程學系/碩士(2013年)

摘要

在電荷比例式數位類比轉換器之二進位電容陣列裡影響電路精確性或效能最關鍵的就是電容比例，如何去產生一組高度對稱並且最小化繞線所產生的寄生效應的共值心電容陣列佈局圖將會是一件相當具有挑戰的研究。但是，絕大多數關於比例是電容陣列的相關研究卻只關注於如何最佳化共值心對稱之佈局，而沒有討論此佈局應用至電荷比例式數位類比轉換器之後的精確性與電路效能。在這篇論文中，我們提出一套有趣且新穎的共值心繞線最佳化之演算法，同步調整電容大小與最佳化寄生效應來提高比例式電容陣列的精確性與效能，並且同時縮小佈局面積與大幅降低功率之消耗。

關鍵字

數位類比轉換器 ； 繞線 ； 擺放 ； 電容 ； 寄生效應 ； 連續漸進式類比數位轉換器

並列摘要

As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the direct routing layout style, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much smaller power consumption.

並列關鍵字

Routing ； Placement ； Capacitor ； Parasitic ； DAC ； SAR-ADC

參考文獻

[1] M. P.-H. Lin, Y.-T. He, V. W.-H. Hsiao, R.-G. Chang, and S.-Y. Lee, “Commoncentroid

capacitor layout generation considering device matching and parasitic minimization,”

IEEE Trans. Computer-Aided Design, vol. 30, no. 23, pp. 32–45, july

common-centroid placement for arbitrary-ratio capacitor arrays considering dummy

capacitors,” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 31, no. 12,