利用掃描鏈重新排序增加橋接錯誤故障涵蓋率架構在低功率固定錯誤樣式填充

Scan reordering for improving bridge fault coverage based on low-power stuck-at-fault pattern fill

郭淳仁(Chun-Ren Kuo)

指導教授 ： 趙家佐

國立交通大學/電機學院/電子工程系所/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.00018

摘要

這篇論文提出掃描鏈的重新排列架構在低功率固定錯誤樣式填充的基礎上，增加橋接錯誤故障涵蓋率。為了克服功率固定錯誤樣式填充所帶來的困難，我們先從物理佈局上面抽出可能的橋接錯誤的發生點，接著利用這些發生點計算每一對PPI在橋接錯誤的可能觸發數，並用這個數字當作每一對PPI的影響力。接著我們提出掃描鏈的劃分以及掃描鏈的重新排列來減少每一條掃描鏈內所有掃描相對間的關聯性，進而提高橋接錯誤故障涵蓋率。最後我們做一些實驗來驗證方法的有效性，繞線的影響也投過實驗來做討論。

關鍵字

掃描鏈 ； 掃描鏈重新排序 ； 橋接錯誤 ； 測試

並列摘要

This thesis proposes a scan reordering method based on low-power fill on stuck-at fault pattern to improve the bridge fault coverage. In order to overcome the drawback of low-power fill on bridge fault coverage, we first extract bridge faults from physical layout and calculate the impact of each PPI pair on bridge-fault activation to measure the correlation between two PPI pair. Next, scan partition and scan reorder are performed to generate scan order that minimizes the correlation hold by scan cells in each scan chain. Experiment shows our proposed method generates better bridge fault coverage comparing to random scan order and the wire length overhead is also provided. Finally, some future possible improvement is presented.

並列關鍵字

Testing ； Scan reorder ； bridge fault ； low-power pattern fill

參考文獻

[1] P. Girard, “Survey of Low-Power Testing of VLSI Circuits”, IEEE Design & Test of Computers, Vol. 19, No 3,pp.82-92, May-June 2002

[4] Sankaralingam, R. Oruganti, R.R. Touba, N.A., "Static compaction techniques to control scan vector power dissipation," VLSI Test Symposium, 2000. Proceedings. 18th IEEE , vol., no., pp.35-40, 2000

[6] Shih Ping Lin; Chung Len Lee; Jwu E Chen; Ji-Jan Chen; Kun-Lun Luo; Wen-Ching Wu; , "A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs," Test Conference, 2006. ITC '06. IEEE International , vol., no., pp.1-8, Oct. 2006

[7] Girard, P.; , "Survey of low-power testing of VLSI circuits," Design & Test of Computers, IEEE , vol.19, no.3, pp.80-90, May/Jun 2002

[8] M. Abramovici, M. Breuer and A. Friedman, "Digital System Testing and Testable Design", IEEE Press, 1990.