氮化矽層內嵌奈米矽晶體之SONOS型記憶體的缺陷分析與電子傳輸機制研究

The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride

何紀瑩(Chi-Ying Ho)

指導教授 ： 陳振芳

國立交通大學/理學院/電子物理系所/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.00452

摘要

本論文為探討氮化矽層內嵌奈米矽晶體之SONOS型記憶體的缺陷分析與電子傳輸機制。首先，我們藉由C-V與DLTS的電性量測與模擬，來探討不同成長條件下其Si-SiO2界面缺陷的密度分佈，發現在氧化層與矽基板接面附近皆有氧化層缺陷(near-interfacial oxide traps)與界面缺陷(interface traps)的存在。由於在薄氧化層元件中
，界面缺陷會導致載子直接穿隧，而造成儲存電荷的流失，因此分析界面缺陷的分布情形可以有助於我們進一步去探討電荷流失的機制。我們採用了高低頻電容法與DLTS量測法，來觀察在矽能隙中不同能量的界面缺陷密度分佈。分析結果得知界面缺陷的密度分佈會與樣品的成長條件有關。通入N2O成長的氧化層由於產生更穩定的Si-N鍵結，因此有更少的界面缺陷；成長較厚的氧化層也可抑制穿隧電流所造成的界面缺陷；另外，我們也發現在成長奈米矽晶體時所放出的氫原子可以修復Si dangling bonds，因此有更佳的界面品質。
同時我們也探討了不同穿隧氧化層厚度的內嵌奈米矽晶體之SONOS型記憶體的電子傳輸機制。從DLTS量測中我們發現，3.0 nm氧化層之樣品會比2.5 nm的樣品存在一個活化能更大的載子放射訊號，並且此訊號是與奈米矽晶體的成長有關，推論氧化層厚度的不同會影響電荷傳輸的機制。我們藉由能帶模擬來計算在不同物理機制(直接穿隧、熱放射、以及缺陷促進穿隧)下載子放射的時間常數。在2.5 nm樣品Si-NCs的載子會先經由熱激發至nitride的本體缺陷ETD，再穿隧到interface traps，最後熱激發至Si導帶；而3.0 nm樣品則會先經由熱激發至nitride的本體缺陷ETD，再繼續熱激發到ETA，最後直接穿隧到Si導帶。3.0 nm的樣品由於穿隧氧化層厚度太厚，因此無法經由穿隧氧化層來放射載子，而是改由熱激發到nitride 本體缺陷ETA的放射路徑，因此放射時間會由nitride bulk trap的熱激發時間所主導。由於3.0 nm載子放射路徑的不同，會有較長的載子放射時間，因此可以提升元件電荷保存能力。
最後，對於元件電荷保存時間的測試，我們使用閘極偏壓加速的方法。隨著逆向偏壓加大與量測溫度的提高，載子的放射時間會隨之變快。當偏壓變大時，內部的電場會因此增加，使得載子穿隧的時間加快；而量測溫度的提高同時也會使得熱激發時間變短。並且，電荷保存時間的量測所得到的數據經由擬合可以得到載子的放射時間，此結果與我們在DLTS量測中所得到的Si-NCs相關訊號的放射時間互相吻合，因此可以確認我們在DLTS所量測到的Si-NCs相關缺陷可以用來儲存電荷。接著我們模擬出低溫下包含儲存電荷的能帶圖。並利用前面提出的2.5 nm載子放射路徑，計算出在Si-NCs放射載子所需的時間常數，會與保存時間所擬合得到的放射時間一致。由此我們可以確立載子的放射途徑，並且了解Si-NCs所形成的缺陷能階確實可以儲存更多電荷以提升元件的保存時間。

關鍵字

奈米矽晶體 ； 電子傳輸 ； 缺陷分析

並列摘要

We analyze the trap states and establish the electron transport model for SONOS memories with embedded Si-NCs in Si3N4. Initially, the distributions of Si-SiO2 interface state density (Dit) under different growth conditions are obtained by capacitance-voltage (C-V) measurements and deep-level transient spectroscopy (DLTS) measurements with the aid of C-V simulations. The interface traps and near-interfacial oxide traps close to Si-SiO2 interface were observed in all samples. When scaling down the tunnel oxide thickness, a corresponding increase of charge loss is observed due to leakage current induced by interface traps. Therefore, the analysis of interface states is essential for the understanding of charge loss mechanism. We utilize high-low frequency C-V method and DLTS measurement to extract the distributions of the interface state density in the Si band gap (EgSi). According to these results, various fabrication processes can cause different distribution of interface trap states. The samples with N2O–grown tunnel oxide have the lowest interface state densities, which is attributed to the formation of more strong Si-N bonds in N2O-grown tunnel oxide layer. For the thick tunnel oxide layer, the interface traps are significantly reduced, and thus the leakage current can be effectively suppressed. In addition, we also elucidate the influence of Si-NCs deposition conditions on the interface state density. The process of Si-NCs formation can reduce the interface state density, which is attributed to the annihilation of Si dangling bonds by residual hydrogen-atom in Si-NCs formation.
Next, we establish the electron transport model for the structures with different tunnel oxide thicknesses. In DLTS measurements, the Si-NCs related signals are observed at all Si-NCs_2 min samples. For the thick tunnel oxide layer, the activation energies of the Si-NCs related traps are larger than others, suggesting a different electron transport process for the thick tunnel oxide layer. Thus, the electron transport mechanism is related to different tunnel oxide thicknesses. According to the band diagram simulation of SONOS with Si-NCs, the electron emission time constants of various mechanisms (direct-tunneling, thermionic, and trap-to-trap tunneling) were calculated. Consequently, we propose two electron transport paths for Si-NCs related signals with different tunnel oxide thicknesses. For 2.5 nm tunnel oxide samples, electrons are thermally activated from Si-NCs related states to nitride bulk traps (ETD), and then tunnel into the SiO2/Si interface states. For 3.0 nm tunnel oxide samples, electrons are thermally activated from Si-NCs related states to nitride bulk traps (ETD), and then are thermally activated from ETD to other nitride bulk traps (ETA), followed by a direct tunneling into the Si conduction band. For thick tunnel oxide samples, the tunneling probability between ETD and SiO2/Si interface states is extremely low, and thus the electron transport path is dominated by thermal activation process from ETD to ETA, resulting in longer electron emission times for Si-NCs related states. These results also indicate that the 3.0 nm tunnel oxide samples have longer retention time than others, which are consistent with the retention measurement results.
We also utilize the retention measurement with applied gate bias to investigate the retention ability of Si-NCs related states. In these measurements, we can obtain the time constant for charge loss of our samples. The obtained time constants of charge loss are consistent with the electron emission time obtained from Si-NCs related states in DLTS measurements. Thus, charge storage in the Si-NCs related states is confirmed. Furthermore, the time constants of charge loss are also in good agreement with the simulation results by utilizing the electron transport model we established. These results can confirm our electron transport model, and also reveal that the formation of Si-NCs actually contribute to charge storage and improve device retention ability.

並列關鍵字

SONOS ； electron transport ； defect analysis

參考文獻

[11] 戴華安, 交通大學電子物理研究所碩士論文, ” 氮化矽層內嵌奈米矽晶體之SONOS型記憶體的分析” (2010).

[1] F. R. Libsch and M. H. White, “Charge transport and storage of low programming voltage SONOS/MONOS memory devices,” Solid-State Electron. 33, 105 (1990).

[2] M. H. White, Y. Yang, A. Purwar, and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Trans.Comp., Packag., Manufact. Technol. A 20, 190 (1997).

[3] E. Suzuki, H. Hayashi, K. Ishii, and Y. Hayashi, “A low-voltage alterable EEPROM with metal-oxide-nitride-oxide-semiconductor (MONOS) structures,” IEEE Trans. Electron Devices 30, 122 (1983).

[4] B. Eitan et al., “Multilevel flash cells and their trade-offs,” IEDM Tech. Dig., pp. 169-172 (1996)