氮化矽層內嵌奈米矽晶體之SONOS型記憶體的分析

The analysis of SONOS memory with embedded silicon nanocrystals in nitride

戴華安(Hua-An Dai)

指導教授 ： 陳振芳

國立交通大學/理學院/電子物理系所/碩士(2010年)

https://doi.org/10.6842/NCTU.2010.00655

摘要

本論文為氮化矽層內嵌奈米矽晶體（Si-NCs）之SONOS型記憶體的電性分析。藉由電容-電壓的模擬可以確認在半導體與氧化層間存在一界面狀態（interface state），並且得到界面狀態濃度與氧化層內固定電荷大小；成長Si-NCs這一過程會減少界面狀態(Dit)，並且增加氧化層內固定電荷(NQss)。
在成長時間Si-NCs 2min的樣品發現，在DLTS的量測中除了界面狀態的訊號，還多了一個額外載子放射訊號。利用能帶圖模擬，發現此額外訊號出現的量測偏壓正好是外質費米能階靠近Si-NCs的導帶的時候，因此推測此訊號跟Si-NCs有關。儲存電荷到Si-NCs 2min的樣品中，並不會影響界面狀態的特性，但對於Si-NCs的內層訊號在DLTS量測到的放射時間會變大，利用能帶圖模擬，建立此訊號的放射機制：從Si-NCs導帶上的電子的允許能階藉著穿隧過氮化矽的缺陷能階(Trap-assisted tunneling，TAT)，再穿隧到半導體與氧化層間的界面狀態，並且包含了熱激發的放射過程。儲存電荷之後載子放射時間變長是由於熱激發放射過程的改變。這個機制證明了Si-NCs的確有在Si-NCs的傳導帶上形成類似量子侷限狀態。成長Si-NCs提供了更多可儲存的狀態，使得記憶窗變大。
有Si-NCs的樣品因為有部分載子儲存在Si-NCs較深的能階上，因此保存能力會比沒有成長Si-NCs的樣品好。我們儲存相同數量的電荷到樣品中，並且假設不同的儲存電荷分佈，模擬Si-NCs 2min、Si-NCs 1min30sec兩個樣品在保存狀態的能帶圖，發現Si-NCs 2min的樣品在氮化矽缺陷能階所要經過的穿隧位能障較低，因此Si-NCs 1min30sec的樣品會比Si-NCs 2min的樣品有擁有更好的載子保存能力。由於不同的電荷分佈，而使得保存能力也有所不同。從量測與模擬的結果指出：在氮化矽層成長Si-NCs的SONOS型記憶體的確造成更多可儲存狀態，並且使儲存的載子保存的更久。

關鍵字

記憶體 ； 奈米矽晶體 ； 保存能力 ； 能帶圖 ； 模擬 ； 電容電壓

並列摘要

We investigate the electrical properties of SONOS memories with embedded Si-nanocrystals（Si-NCs） in Si3N4. The capacitance-voltage（C-V） simulations identify the interface states at Si-substrate/SiO2 interface. Simulation results also obtain interface state density (Dit) and amount of fixed oxide charges (NQss). The process of Si-NCs formation can reduce the interface state density and increase the amount of fixed oxide charges.
In deep level transient spectroscopy （DLTS） measurement, the Si-NCs 2min sample appears an extra signal beside interface states signal. The band diagram simulation reveals that the extrinsic Fermi-level is close to Si-NCs conduction band when the extra signal is measured. These results demonstrate that the extra signal is originated from the Si-NCs. After programming carriers into Si-NCs 2min sample, the interface states signal is nearly unchanged, and the emission time constant of Si-NCs related signal is increased. According to the band diagram simulation, we propose the emission mechanism of Si-NCs related signal: Electrons tunnel from Si-NCs to nitride bulk trap, and then tunnel from nitride bulk trap to interface states ( trap-assisted tunneling (TAT)). The TAT process includes thermal emission process. The increase of emission time constant after programming is due to the conversion of thermal emission process. This emission mechanism also reveals the existences of quantum confined states above Si-NCs conduction band. Thus, embedded Si-NCs in Si3N4 act as a formation of Si-quantum dots in Si3N4, and provide more programmable states for SONOS memory.
Retention abilities of embedded Si-NCs samples are better than SONOS. The difference of retention abilities is due to parts of programmed carriers are stored in Si-NCs. We program the same amount of carriers into samples, and we assume different distributions of programmed carriers in Si-NCs 1min30sec and Si-NCs 2min samples. Si-NCs 2min sample stores more carriers in Si-NCs than Si-NCs 1min30sec sample. Band diagram simulation demonstrates that the tunneling barrier is lower in Si-NCs 2min sample than in Si-NCs 1min30sec sample. The difference of tunneling barriers results Si-NCs 1min30sec sample has better retention ability than Si-NCs 2min sample. Different distributions of storage carriers result different retention abilities. The results of experiments and simulations reveal Si-NCs in Si3N4 produce more programmable states and enhance carrier retention abilities.

並列關鍵字

SONOS ； nanocrystal ； retention ； band diagram ； simulation ； CV

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