利用共鍍催化金屬預先成長奈米碳管基之矽晶直通孔於三維積體電路應用之研究

Study on the CNT-first-approach Technology of Carbon Nanotube-based Through Silicon Vias with Co-deposited Catalytic Metals for Three Dimensional Integrated Circuits

江俊賢(Chun-Hsien Chiang)

指導教授 ： 鄭裕庭 ； 鄭晃忠

國立交通大學/電機學院/電子工程系所/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.00825

摘要

近年來，隨著元件微縮在製程上遭遇瓶頸，積體電路在元件密度的提升速度上逐漸趨於緩慢，基於元件微縮不再能滿足摩爾定律的要求，三維積體電路(Three Dimensional Integrated Circuits, 3D-ICs)的概念遂被引進。三維積體電路具有異質整合以及晶片堆疊的優勢，被認為將是未來滿足摩爾定律的選擇之一，而作為晶片之間互相連結的內導線，矽晶直通孔(Through Silicon Vias, TSVs)在三維積體電路中扮演了極為重要的角色，傳統上，由於銅具有良好的導電特性，矽晶直通孔通常藉由電鍍銅的方式來填充金屬作為內導線使用，然而隨著矽晶直通孔的高寬比急遽增加，填充銅的難度也相對的提升。我們為了完成具有較大高寬比值、低電阻的矽晶直通孔內導線，而採用共鍍催化金屬的方法來控制成長之奈米碳管的密度，希望能藉由增加奈米碳管密度進而降低矽晶直通孔的電阻，並且採用在沉積介電質之前預先成長奈米碳管的方式(CNT-first Approach)製作出以奈米碳管作為基礎之矽晶直通孔導線。
我們藉由調整共鍍催化金屬鈷鈦的比例在1:3, 1:1, 3:2 以及 3:1的情況下來控制催化金屬的分布，試圖找出最好的共鍍金屬比例以獲得同時具有最小尺寸以及分佈密度最高的奈米催化金屬粒子，並且透過調整奈米碳管成長中所通入的碳源氣體乙烯和氫氣之間的比例，找出最佳的條件以成長高度能達到50 ~ 70微米的奈米碳管束以符合矽晶直通孔的高度需求。藉由控制催化金屬鈷鈦比例在1:1，以及通入100 sccm的乙烯和100 sccm的氫氣作為成長氣體的情況下，我們成功的成長出具有高度50 微米以上高度且奈米碳管管壁密度高於1012 cm-2的奈米碳管束以應用於製作以奈米碳管作為基礎之矽晶直通孔。
直接在奈米碳管束旋塗SU-8介電質有可能造成奈米碳管本身的形變，也因此我們先使用一層氧化層包覆奈米碳管束再旋塗SU-8，藉此防止在塗佈SU-8介電質時造成奈米碳管束發生形變，當此氧化層厚度為 2微米時，奈米碳管將會在接續的研磨過程中遭到撕扯進而導致整個導線結構的破壞；所以改使用1微米的 TEOS氧化層，可以讓SU-8介電質滲入奈米碳管束中作為支撐層以防止奈米碳管在研磨時的形變。
在成功的預先成長奈米碳管製作出奈米碳管基之矽晶直通孔，並且藉由量測不同高度下的矽晶直通孔計算出我們的奈米碳管束具0.43 Ω‧cm的電阻率，我們同時發現在奈米碳管束底層之金屬以及矽基版之間產生了蕭特基接面(Schottky Contact)，為了減輕蕭特基接面對於整體電阻造成的影響，我們將試片加熱並且發現量測出的電阻呈現歐姆特性，並且可以在攝氏200度的情況下將整體電阻率降至0.34 Ω‧cm，意味著我們可以除去蕭特基接面對電阻所造成的影響。此種方法成長出的奈米碳管本身因兼具良好的特性與簡單的製程所以極適用於三維積體電路中的矽晶直通孔應用。

關鍵字

奈米碳管 ； 矽晶直通孔 ； 三維積體電路

並列摘要

In recent years, the enhancement of packing density through device scaling-down became slower because the scaling down of devices have met numerous bottlenecks in practical fabrication process. Since Moore’s law could not be satisfied by device scaling-down, the concept of three dimensional integrated circuits (3D-ICs) has been introduced. On account of the advantages of heterogeneous integration and chip stacking, 3D-ICs have been regarded as one of the options to achieve the trend of Moore’s law. Among the technologies of 3D-ICs, through silicon vias (TSV) played a crucial role in the connections between each chips. Nowadays, TSVs were usually filled with copper by conventional electroplating because of the low resistivity of copper. However, since the rapid increasing of TSV aspect ratios, the difficulty of TSV copper filling has also been increased. To realize the TSVs with high aspect ratio and low electrical resistivity, new materials must be taken into consideration. Therefore, carbon nanotubes (CNTs) have been thought as one of the promising materials in TSVs. In this thesis, co-deposited metals have been used to control the density of catalyst nanoparticles, and achieve high density of CNT bundles. The resistance of CNT-based TSVs is expected to be reduced with the dense CNT bundles. Our purpose is to establish CNT-first approach for CNT-based TSVs with high aspect ratio and low electrical resistivity for 3D-IC applications.
By setting the ratios of co-deposited Co-Ti metals to be 1:3, 1:1, 3:2 and 3:1, the distribution of catalyst nanoparticles could be controlled. Co-deposited catalyst nanoparticles with smallest size and highest density would be regarded as the best solution to grow CNTs. Ethylene (C2H4) and hydrogen (H2) were used as the growth gases for growing CNTs. The ratio of ethylene and hydrogen was also optimized to grow aligned CNTs with the height of 50 ~ 70 um for the application of TSVs. By controlling the ratio of co-deposited Co-Ti metals to be 1:1, the wall density of CNTs exceeding 1012 cm-2 could be obtained. Then, CNT bundles with the height higher than 50 um could be achieved by using the optimized flow rates of 100 sccm ethylene and 100 sccm hydrogen. The CNTs bundles with high wall density and the height of 50 ~ 70 um could be achieved for CNT-based TSVs.
Deformation of CNT bundles would be occurred by directly depositing SU-8 dielectric layer on CNT bundles. By covering the CNT bundles with an oxide film before SU-8 dielectric layer spin coating, SU-8 dielectric layer could be blocked and the deformation of CNT bundles could be avoided. As the thickness of TEOS-oxide was increased to 2 um, CNT bundles would be tor into pieces during polish process and the TSV structures would be broken. Therefore, the TEOS-oxide with 1 um in thickness was used. SU-8 dielectric layer would infiltrate into CNT bundles as a supporting layer and the deformation of CNT bundles during polishing process could be avoided.
In this thesis, CNT-first approach of CNT-based TSVs has been achieved. The resistivity of our CNT bundles could be obtained to be 0.43 Ω‧cm by measuring TSVs with different via heights. Schottky contact has been found between silicon substrate and the bottom metal layer Ti under CNT bundles. To reduce the influence of Schotkky contact , CNT-based TSVs have been heated to 200 ℃. Ohmic behaviors have been found and the resistivity could be reduced to 0.34 Ω‧cm at 200 ℃. It means if the Schottky contact could be removed from our structure, the CNT-based TSVs with excellent characteristics and simple fabrication process produced by utilizing CNT-first approach could be obtained, and could be applied in the 3D-ICs.

並列關鍵字

Carbon nanotubes (CNTs) ； Through silicon vias (TSVs) ； Three dimensional integrated circuits(3D-ICs)

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