微波寬頻CMOS混頻器之設計

Microwave Wideband CMOS Mixer Design

曾珮玲(Pei-Ling Tseng)

指導教授 ： 高銘盛

國立交通大學/電機學院/電信工程系所/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.00844

摘要

本論文主要探討在毫米微波接收機中兩個重要的高頻電路，一個是超寬頻降頻器，另一個是倍頻器，最後再將此兩個電路結合做分析研究。
第一部分:設計一個應用於W-Band 接收機的降頻器，首先會先簡單介紹W-Band接收機的系統架構，之後將提出所設計的寬頻降頻器。該降頻器輸入頻段為17.4~26.1GHz，利用LO訊號為17.4GHz，將此頻段的訊號降頻到DC~8.7GHz。該降頻器有將近10GHz的IF頻寬，Conversion Gain 為0dB。此外該降頻器會使用到兩個Balun，分別將RF和LO訊號分成差動訊號，因此在降頻器中加入兩個on chip的Balun，並且將對Balun做探討。同時因為IF端有將近10 GHz的頻寬(單端輸出)，所以我們必須設計寬頻且高CMRR的IF端電路。該IF端電路有20dB以上的CMRR在DC~8.7 GHz頻段內。
第二部分:利用二倍頻乘法器將LO訊號由8.7GHz升頻到17.4GHz，此電路有良好的頻譜乾淨度，可抑制8.7、26.1GHz的unwanted harmonics。該倍頻器是使用TSMC 0.18um mixed signal/RF process，在2V電壓下，能提供6dB conversion gain，輸出功率為4dBm，晶片面積為0.98mm 。
第三部分:為了減輕LO模組的設計負擔，我們將LO倍頻器整合至降頻器中，中間用Marchand balun將倍頻器LO訊號轉成差動訊號匯入mixer core。其RF、LO、IF端的輸入反射係數均低於-10dB，並且擁有2dB的轉換增益而線性度(IIP3)至少大於3dBm，雜訊為11~14dB。

關鍵字

混頻器 ； 倍頻器 ； 微波

並列摘要

This thesis discusses two high frequency circuits applied in millimeter wave receiver. One is a wide band down-converter and the other is a doubler. Then will this combination of two circuit analysis study.
In part one, a wide band down converter will be designed for W-band receiver. First a W-band receiver architecture will be introduced and one of the down-converter in the receiver will be proposed. The part describes the development of the down-converter, with the RF frequency chosen to be 17.4~26.1GHz, LO fix at 17.4GHz and IF close to DC~8.7GHz. The down converter can achieve about 10 GHz IF bandwidth and conversion gain 0 dB. There will be two on-chip baluns implemented in the circuit for converting single RF and LO signals to differential signals and the balun will be discussed. Besides the down-converter has 10 GHz IF-bandwidth, the IF stage circuit must provide high CMRR over the bandwidth. In the proposed circuit the IF stage can achieve above 20dB CMRR in DC~8.7 GHz.
In part two, frequency doubler will rise LO signal from 8.7GHz to 17.4GHz. The circuit has a distinct spectrum, can suppress the 8.7GHz and 26.1GHz of unwanted harmonics. The doubler is designed based on CMOS TSMC 0.18um mixed signal/RF process. With 2V supply voltage, the doubler has the conversion gain of 6 dB; output power of 4 dBm. The die size of 0.98mm .
In part three, in order to reduce the difficulty in designing the corresponding LO module, the mixer with the integrated LO frequency doubler has been proposed. Marchand balun is to be used among mixer and doubler for converting single LO signal to differential signal. The designed circuit has RF, IF, and LO input return loss below -10 dB; conversion gain of 2dB; the noise figure of 11~14dB; and the IIP3 above 3dBm.

並列關鍵字

mixer ； doubler ； Microwave

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