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  • 學位論文

超低動態電壓基於頻率比之製程、電壓、溫度感測器與其應用

Ultra-low Dynamic Voltage Scaling Fequency-Ratio-Based PVT Sensor Design and Applications

指導教授 : 黃威

摘要


隨著製程不斷微縮,高密度的積體電路造成自我加熱的問題。為了有效進行溫度管理,本論文提出了一種適應性電壓選擇的製程電壓溫度變異感測器,其操作的電壓範圍從0.25 V〜0.5V,具備了2.3μW功耗和50K採樣 /秒的轉換率。接著,0.4V的完全晶上抗製程變異溫度感測器被提出,製程變異造成的影響顯著降低。該電路經過實現且運作在0.4V電源電壓下,運行的溫度範圍為 0˚C至100˚C。此溫度感測器核心面積(不包括 輸入/輸出阜)只有990μm2。電力消耗量的轉換率是11.6μJ/採樣。所有這些特點使溫度感測器適用於能源有限與能源收穫微型便攜式平台。最後,三維集成電路(3D- IC)架構被提出。為了防止內部各層的熱點效應與減少動態隨機存取記憶體刷新功率,我們運用抗製程變異溫度感測器,提出了一個動態隨機存取記憶體刷新控制器。由於溫度感測器功耗很小,刷新控制器之額外功率不大,且有效減少67.67%之待機功耗。

並列摘要


With process scaling down continuously, high level of integration introduces the problem of self-heating. To perform thermal management, this thesis proposes 0.5V~0.25V process voltage and temperature (PVT) sensors with adaptive voltage selection operating over an ultra-low supply voltage range from 0.25V~0.5V with 2.3μW power consumption and 50k samples/sec conversion rate. Next, the 0.4V fully integrated process invariant temperature sensor is proposed. The effect of process variation is significantly reduced. The realization meets the target to be capable of 0.4V supply voltage operation over the temperature range of 0˚C to 100˚C. The area of the sensor core (without I/O pads) is only 990μm2. The power consumption per conversion rate is 11.6pJ/sample. The high area/energy efficiency characteristics make the proposed sensor applicable for energy-limited miniature portable platforms. Finally, the heterogeneous three dimension integrated circuit (3D-IC) architecture is presented. To prevent hot spot on the intra layer and reduce refresh power on DRAM layer, we proposed a DRAM refresh controller utilizing the process invariant temperature sensor. Thanks for tiny power consumption of temperature sensors, the refresh controller reduces standby power significantly, 67.67% without much power overhead.

參考文獻


Chapter 1
[1.1] S. K. Gupta, A. Raychowdhury and K. Roy, “Digital computation in subthreshold region for ultralow-power operation: a device-circuit-architecture codesign perspective,” in Proceeding of the IEEE, pp. 160-190, Feb. 2010.
[1.2] B. H. Calhoun, J. F. Ryan, S. khanna, M. Putic, J. Lach, “Flexible circuits and architectures for ultralow power,” in Proceeding of the IEEE, pp. 267-282, Feb. 2010.
[1.4] W. H. Cheng and B. M. Baas,” Dynamic Voltage and Frequency Scaling Circuits with Two Supply Voltages,” in IEEE Int’l Symp. Circuits and Systems, pp. 1236-1239, June 2008.
[1.5] V.F. Pavlidis, E.G. Friedman, "Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits, " in Proceedings of the IEEE , vol.97, no.1, pp.123-140, Jan. 2009.

被引用紀錄


吳富榮(2009)。保全業標準作業流程與風險管理研究〔碩士論文,國立臺北大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0023-1401200913582100
卓冠伯(2016)。保全業經營者因應物聯網發展之策略研究〔碩士論文,國立臺北大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0023-1303201714241927

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