近/次臨界靜態隨機存取記憶體為基礎的先進先出記憶體設計於近身無線網路的設計和實作

Design and Implementation of Near-/Sub-threshold SRAM-based First-In-First-Out (FIFO) Memory for WBAN Application

杜威宏(Wei-Hung Du)

指導教授 ： 黃威

國立交通大學/電機學院/電子工程系所/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.01005

摘要

因為功率消耗的增減會以平方倍的方式隨著電源電壓的縮減，因此超低電壓電路設計成為一個重要研究課題。然而，在低電壓的區域，大幅增加的電路參數敏感度會限制靜態隨機存取記憶體的運行。因此，在極低電壓下，穩定性是最需要被關注的。在本論文中，首先提出一個10T近/次臨界隨機存取記憶體存儲單元，比起傳統的隨機存取記憶體，它有1.9倍的讀取靜態雜訊邊界，3.2倍的寫入邊界及較好的變異抵抗力，並且降低資料相依的位線漏電流與更好的溫度變化容忍度，以90奈米技術下十萬次的Monte Carlo 模擬結果顯示，比起其他等面積的雙埠隨機存取記憶體存儲單元，這個10T的記憶體單元可具備最低的Vmin能力。接著以聯電90奈米技術實現以隨機存取記憶體為基礎的一個極低功率16kb先進先出記憶體應用於近身無線網路，這個先進先出記憶體有高變異抵抗力可容許操作在極低電壓區域，他採用自適應功率控制和電源閘系統，以計數器為基礎的指標，和一個智能仿製讀寫控制裝置來達到極低功耗。在0.5V電壓下，此設計每讀寫一次僅需平均消耗1.646微瓦。同時，以台積電65奈米技術來實作一個2kb內置排控動態電源調整9T隨機存取記憶體為基礎的先進先出記憶體。一個內置排控的自適應電源切換控制電路會轉換兩種操作電壓，0.5V和0.3V，來達成高性能和低功率的應用。此提出的內置排控動態電源調整先進先出記憶體消耗0.529微瓦的平均功率，在接收時段和傳輸時段分別可以和無使用此技術相比省下49.3%和18.5%的功率。

關鍵字

隨機存取記憶體 ； 先進先出記憶體 ； 低功率 ； 次臨界 ； 近臨界 ； 近身無線網路

並列摘要

The power consumption is reduced quadratically by supply voltage scaling down. However, the effect of environment variations on MOSFETs characteristics is too severe to degrade the SRAM operation robustness in low voltage regime. Hence, reliability is the major concern in ultra-low voltage. In this thesis, a 10T sub/near-threshold SRAM bit-cell is proposed firstly, which has 1.9X read SNM, 3.2X write margin, and reduces data-dependent bit-line leakage with better temperature variation tolerance. Simulation results on 100,000 times Monte Carlo simulation in UMC 90nm CMOS technology show that our 10T bit-cell gives the minimum Vmin compared to the other iso-area successful bit-cells. Secondly, an ultra-low power 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). With high variation immunity, this FIFO memory is capable of operating in ultra-low voltage regime, which features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. At 0.5V supply voltage, the proposed design consumes 1.646μW in average per read/write operation. Thirdly, a 2Kb built-in row-controlled DVS 9T SRAM-based FIFO memory is implemented in TSMC 65nm technology. A row-based adaptive power switch control system transforms two supply voltages, 0.5V and 0.3V, for energy-constrained applications. The proposed built-in row-controlled DVS FIFO consumes 0.529μW average power, which can provide 49.3% power savings in receiving time and 18.5% power saving in transmitting time compared to those without it.

並列關鍵字

SRAM ； FIFO ； low power ； sub-threshold ； near-threshold ； WBAN

參考文獻

Chapter 1

[1.1] S. K. Gupta, A. Raychowdhury, and K. Roy, “Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective,” IEEE Proceeding, vol. 98, issue 2 Feb. 2010, pp. 160-190.

[1.3] W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Trans. Electron Devices, vol. 53, no. 11, Nov. 2006, pp. 2816–2823.

[1.4] Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y.-G. Ng, L. Wei, Y. Zhang, K. Zhang and M. Bohr, “A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management,” in IEEE JSSC, vol. 45, no. 1, Jan. 2010, pp. 103-110.

[1.5] S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS,” IEEE Trans. Comput.–Aided Design (CAD) integer. Cricuit Syst.,vol. 24, no. 12, Dec. 2005, pp. 1859–1880.