高壓製程之靜電放電防護元件設計

Study of Electrostatistic Discharge Protection Devices in High-Voltage BCD Processes

黃楀晴(Yu-Ching Huang)

指導教授 ： 柯明道

國立交通大學/電機學院/電子工程系所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00080

摘要

高壓元件已在各種產品(電腦、消費性、通訊、和車用電子產品)中被廣泛的運用，LED、車用安全控制晶片、電源管理晶片、觸碰螢幕控制晶片和太陽能元件都是很好的例子，將來這樣的應用將會與IC產業的緊密結合。隨著高壓元件市場需求量日與劇增，連帶的對於高壓元件的靜電放電防護可靠度設計的需求也非常高。在積體電路製造、封裝及測時的時候，都有可能受到靜電的轟擊，隨著元件尺寸縮小，這樣的危害更為明顯。現今，靜電放電所造成的可靠度議題漸漸的被重視。為了避免靜電來襲將會導致元件不正常工作甚至損壞，添加或更改元件結構使其滿足靜電防護的標準將是一個十分重要的課題。 在高壓製程中靜電防護的研究尤為困難。因為高壓的靜電放電防護元件需同時滿足耐高壓及大電流的能力，又要防止閂鎖效應 (latch up)的發生。橫向擴散電晶體(LDMOS) 常在高壓互補式金氧半製程中被使用，倘若其能同時工作和當作靜電防護元件將會省去許多面積。然而，在高壓製程中有諸多變因會導致靜電防護能力的下降，例如克爾克效應 (Kirk-effect)導致保持電壓(holding voltage)太低、元件的不均勻導通：導致電流過於集中某處所造成永久性的損害、氧化層的載子侷限效應(oxide charge trapping)等等造成其高壓元件本身難有良好之靜電放電防護能力，在這個因素之下，即使將靜電放護元件布局面積放大，也不一定會獲得耐受度的提升。不均勻導通的原因，有可能是因為其保持電壓太低的緣故，提升元件的保持電壓，既可能可以改善不均勻導通的現象，也能夠防止雜訊導致的閂鎖效應，但由於熱的效應，提升電壓很容易導致可排放之靜電放電電流下降。因此如何在不減損原本靜電防護能力的前提之下提高其保持電壓，也是高壓靜電防護元件設計的一大課題。 如何設計最佳化的高壓靜電放電防護元件，是本論文的探討重點。在這次碩士論文，提出了許多不同結構形式的橫向擴散電晶體(LDMOS)，希冀能透過研究，找出橫向擴散電晶體的最佳結構能夠滿足同時正常工作和自我保護的要求。其透過第三章的研究結果可以發現，在汲極端加以改良設計過後的元件能成功的使寄生的矽控整流器(SCR)成功的出現，也因此該元件的靜電耐受度能夠過人體放電測試2kV的 靜電防護標準。另外，先前提到的不均勻導通及閂鎖效應均歸因於保持電壓太低，這個問題尤以含有寄生矽控整流器的元件中最為明顯。因此有許多提升保持電壓的方法將在本論文的第四章中被提出，透過實際下線量測的結果可以發現，在源極中多加上一個寄生雙極性電晶體的結構能夠使保持電壓有效的提升，搭配其他參數的變化，就能夠發展出許多不同的靜電防護元件。本碩士論文所提出結構也已經有相對應的國際期刊與會議論文發表。

關鍵字

靜電防護

並列摘要

Nowadays, with a rapid increase in demand, such as motor drivers, LED lighting, solar energy and display driver circuits, high voltage integrated process technologies have been developed and become commercially available. The lateral DMOS (LDMOS) is a common device for high-voltage output driver. Thus, LDMOS was expected for self-protection electrostatic discharge (ESD) device. ESD is an inevitable event during fabrication, packaging and testing processes of integrated circuits. ESD protection design is therefore necessary to protect ICs from being damaged by ESD stress.
In the last two decades, some studies shows that ESD robustness of nLDMOS is not good in the results of Kirk-effect-induced holding voltage lowering, multi-finger non-uniformity issue and isolation oxide charge trapping issue. Though the ESD performance is not good enough, gate-grounded-LDMOS in ESD condition is widely used due to straightforward implementation and sufficient high current capabilities. Developing a HV-LDMOS that can meet the acceptable ESD level without scarifying the IV characteristics and dimension of the device will be a big challenge for smart power technologies.
In this work, many different structures of nLDMOS have been realized in 0.25-μm 60-V BCD process including source-side and drain-side engineering. Also stretch the layout parameter and style to optimize the nLDMOS’s ESD robustness. The structure that combines the concepts of changing the layout space and embedded SCR inside LDMOS with additional p+ and n+ implantation regions between its drain and poly-gate to make sure that it can keep stably in the high-current holding region and meet the typical ESD specification of commercial IC products.
Owing to the superior ESD performance of SCR, the device structure in Chapter 4 is based on embedded SCR structure in both HV and LV well. Hoping to figure out a device that can have good ESD levels and latchup immunity, this work investigates the different structures and parameters of HVSCR and LVSCR by many different methods to increase the holding. All the devices are successfully verified in a 0.25-μm 60-V BCD process.

並列關鍵字

ESD

參考文獻

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