高速響應低功率數位控制低降壓穩壓器整合高速隨機存取記憶體

An Ultra-Fast Response and Low Power Digital Low Dropt Output for High Speed Embedded Memory

劉正忠(Cheng-Chung Liu)

指導教授 ： 陳科宏

國立交通大學/電機學院/電機學院電機與控制學程/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00501

摘要

本文主要於討論應用在高速響應和低功率的數位控制低降壓穩壓器整合一傳統降壓電路與高速隨機存取記憶體晶片，此數位控制低降壓穩壓器晶片是由一參考電壓電路模組，功率電晶體模組和時序控制模組所組成，而數位控制低降壓穩壓器是一低靜態電流，低功率消耗運作，不需外加大電容且能快速響應。
關於功率電晶體模組是由兩個功率電晶體所組成並分成主要電源供應與次要電源供應，主要電源供應的功率電晶體提供大部份的功率消耗，次要電源供應的功率電晶體做為備用以支援主要功率電晶體為目的不需要時關閉完全不耗電，來達到節能效果此時所需要的供電需求來自參考電壓電路模組。
至於傳統線性調整器因為運算放大器反應速度較慢，功率消耗較大且需要外掛等效串聯電阻低的大電容來做頻率補償及減少負載變化時電壓的變化使得系統更穩定。

關鍵字

數位控制低降壓穩壓器 ； 靜態隨機存取記憶體

並列摘要

This work discussed the proposed digital LDO(Low Drop Output) application to high speed response and low power consumption, and integrate conventional LDO with the SRAM IP modulated. The proposed low quiescent current digital LDO with wide range operating voltage consists of a VREF generator module, power MOS module and timing control block module. It exhibits the low power consumption operation to realize the Ultra-Fast response without low ESR capacitor.
Regarding the power MOS module consisted of two power MOS components. The main power MOS supply most of the system power consumption and the second power MOS provide while the system power shortage. The power MOS shut down without power consumption while idle to achieve power savings, and VREF module provides the power needed. The conventional LDO needs the external components for the large value capacitors to place the zero in desired location to stabilize the system. This work use low quiescent current, low-voltage operation and low capacitor compensation of proposed digital LDO to achieve Ultra-Fast response for high speed embedded memory on SOC chip.
To verify this system, using USB2.0 front-end interface, 5sets GPIO back-end interface with per set has 0~7 ports and total 40 ports MCU chip to read/write SRAM, and via design PCB board probe pin to measure and monitor voltage deviation, current waveform. This USB2.0 controller needs the definition of each port function, and then through PC software AP to commands read/write action to compare the difference of DLDO and Conventional LDO.

並列關鍵字

Digital Low Dropt Output ； SRAM

參考文獻

[2] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGRAW-HILL, 2001.

[3] Rincon-Mora, G.A. “Active capacitor multiplier in Miller-compensated circuits”, Solid-State Circuits, IEEE Journal, Vol. 35, pp.26-32, Jan. 2000.

[4] Yu-Huei Lee, et al., “A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance,” VLSI Circuits (VLSIC), pp. 178-179, June 2012.

[5] Yu-Huei Lee, et al., “A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System,” IEEE J. of Solid-State Circuits, vol. 45, pp. 2227-2238, Nov. 2010.

[6] Onouchi, M. et al., “A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process,” Solid State Circuits Conference (A-SSCC), pp. 37-40, Nov. 2011.