基於量測電晶體特性之預測曝光層級靜態隨機存取記憶體讀寫容限

Predicting Shot-Level SRAM Read/Write Margin based on Measured Transistor Characteristics

賓恕雍(Shu-Yung Bin)

指導教授 ： 趙家佐

國立交通大學/電機學院/電子工程系所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00986

摘要

靜態隨機存取記憶體陣列測試結構可直接測量陣列中每個靜態隨機存取記憶體單
元的讀寫能力和單元中每個電晶體的特性，然而測量記憶體單元的讀寫能力的總
測試時間比測量記憶體單元中每個電晶體特性的時間更長。本論文提出模型擬合
流程利用量測出的電晶體特性來預測靜態隨機存取記憶體在單一光罩中的平均讀
寫能力。本文所提出的流程透過對4750 個樣本的測量結果驗證，每個樣本包含
128 位元的靜態隨機存取記憶體陣列測試結構，使用聯電28 奈米制程工藝實現。
實驗結果顯示，該擬合模型在擬合曝光層級之靜態讀取雜訊邊界、寫入邊界及讀
取電流可以達到至少97.77％的決定系數，模型使用2375 個樣本的測試數據。

關鍵字

靜態隨機存取記憶體 ； 陣列測試結構 ； 測試時間縮減 ； 模型擬合

並列摘要

An SRAM-array test structure provides the capability of directly measuring
the characteristics of each transistor and the read/write metrics for each SRAM cell
in the array. However, the total test time of measuring the read/write metrics takes
longer than that of measuring each transistor’s characteristics. This thesis presents
a model-fitting framework to predict the average read/write metrics of the SRAM
cells in a lithography shot by using only the measured transistor characteristics. The
proposed framework is validated through the measurement result of 4750 samples of a
128-bit SRAM-array test structure implemented in a UMC 28nm process technology.
The experimental results show that the learned models can achieve at least 97.77%
R-square on fitting the shot-level read static noise margin, write margin, and read
current based on a 2375-sample testing data.

並列關鍵字

SRAM ； array test structure ； test time reduction ； model-fitting

參考文獻

”Characterization of bit transistors in a functional SRAM,” IEEE Symposium

[3] Z. Guo, A. Carlson, L.-T. Pang, K. T. Duong, T.-J. K. Liu and B. Nikolić,

”Large-Scale SRAM Variability Characterization in 45 nm CMOS,” IEEE

Journal of Solid-State Circuits, vol. 44, No. 11, pp. 3174-3192, 2009.

characterization scheme for CMOS 6T SRAM array,” IEEE International